Verifying logic synthesizers

A method of generating a plurality of input vectors for use in simulating a netlist, the method comprising:

• receiving an HDL mode;
• generating a netlist and an information file from the HDL model using a synthesizer;
• and
• receiving a parameter file, wherein the parameter file comprises information relating to generating a plurality of input vectors;
• and
• generating the plurality of input vectors using the information file and the parameter file,
• wherein the information file comprises information relating to a plurality of input and output pins of the netlist, wherein the information relating to at least one input pin in the plurality of input and output pins relates to whether the input pin should typically have a logic level that is high, low, or random, and wherein the plurality of input vectors are such that no two input signals change state simultaneously.

A method of verifying a logic synthesizer comprising:

• for each of a plurality of HDL models:
• generating a first netlist from an HDL model using a first synthesizer capable of synthesizing the first netlist from the HDL model to generate a first synthesizer logic design;
• generating a second netlist by place and routing the first netlist to fit an integrated circuit layout;
• modifying the first synthesizer logic design to generate a second synthesizer, wherein the functional operation of the second synthesizer corresponds to the functional operation of the first synthesizer;
• generating a third netlist from the HDL model using the second synthesizer;
• generating a fourth netlist by place and routing the third netlist to fit the integrated circuit layout;
• simulating the second netlist using a plurality of test vectors derived from the first synthesizer to generate a first plurality of output vectors;
• simulating the fourth netlist using the plurality of test vectors to generate a second plurality of output vectors;
• comparing the first plurality of output vectors with the second plurality of output vectors;
• and
• determining whether or not any difference found between the first plurality of output vectors and the second plurality of output vectors is due to corresponding circuits associated with the second netlist and the fourth netlist that generate different output vectors from the test vectors.

A method of verifying a place and route program comprising:

• generating a first netlist using a synthesizer;
• generating a second netlist by place and routing the first netlist using a first place and route program to fit an integrated circuit layout;
• generating a third netlist by place and routing the first netlist using a second place and route program to fit the integrated circuit layout, wherein the second place and route program is derived from the first place and route program;
• generating a first set of output vectors by simulating the second netlist using a set of input vectors;
• generating a second set of output vectors by simulating the third netlist using the set of input vectors;
• comparing the first set of output vectors and the second set of output vectors;
• and
• determining if any difference between the output vectors are caused by correctly routed second netlist and third netlist that generate different output vectors in response to the set of input vectors.

A method of verifying a logic synthesizer comprising:

• for each of a plurality of HDL models:
• generating a first netlist from an HDL model using a first synthesizer configured to generate the first netlist in response to logic circuitry data of the HDL model;
• simulating the first netlist using a plurality of test vectors to generate a first plurality of output vectors;
• modifying a logic design of the first synthesizer to generate a second synthesizer, wherein the functional operation of the first synthesizer and the second synthesizer is the same;
• generating a second netlist from the HDL model using the second synthesizer;
• simulating the second netlist using the plurality of test vectors to generate a second plurality of output vectors;
• comparing the first plurality of output vectors with the second plurality of output vectors;
• and
• determining if any differences found from the comparison of the plurality of output vectors to the second plurality of output vectors are caused by corresponding logic designs functions of the first synthesizer and the second synthesizer that are functionally equivalent.

A method of verifying a logic synthesizer comprising:

• for each of a plurality of HDL models:
• generating a first gate level netlist from an HDL model using a first synthesizer;
• simulating the first netlist using a plurality of test vectors to generate a first plurality of output vectors;
• generating a second gate level netlist from the HDL model using a second synthesizer, wherein the second synthesizer is generated by modifying logic circuits of the first synthesizer and wherein the second synthesizer is configured to provide the same input/output function as the first synthesizer;
• simulating the second gate level netlist using the plurality of test vectors to generate a second plurality of output vectors;
• comparing the first plurality of output vectors with the second plurality of output vectors;
• and
• determining if any errors found in the comparison are due to corresponding logic circuits of the first synthesizer and the second synthesizer that are functionally the same but generate different output vectors.

A method of verifying a logic design synthesis comprising:

• generating an initial netlist from a first logic synthesis model;
• generating a set of initial test vectors from the initial netlist;
• simulating the initial netlist using the set of initial test vectors;
• modifying a first logic circuit design of the first logic synthesis model to generate a second logic synthesis model;
• generating a second netlist from the second logic synthesis model;
• simulating the second netlist with the set of initial test vectors to generate a second set of test vectors;
• comparing the initial set of test vectors and the second set of test vectors to determine a difference therebetween;
• and
• determining if any differences in the initial set of test vectors and the second set of test vectors are due to differences in output vectors generated by initial logic circuits of the initial logic synthesis model and corresponding second logic circuits of the second logic synthesis model, wherein the initial logic circuits and the second logic circuits are functionally equivalent.