Multi-threshold-voltage integrated circuit having a non-volatile data storage circuit

An integrated circuit comprising:

• a sleep switch, provided between a first power supply line and a second power supply line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, the first and second power supply lines and the sleep switch being provided on each of a high power supply line side and a low power supply line side:
• a latch circuit, connected to the second power supply line on said high power supply line side and the second power line on said low power supply line side, which is constituted by a transistor of a second threshold voltage which is lower than said first threshold voltage;
• a ferroelectric capacitor for storing data held in said latch circuit in accordance with polarization direction of a ferroelectric film thereof;
• and
• a control signal generating circuit which, when returning to an active mode from said sleep mode, generates a plate signal for driving a terminal of said ferroelectric capacitor to generate a voltage in said latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the pair of sleep switches on said high power supply line side and low power supply line side to conduct to thereby activate said latch circuit following the driving of said ferroelectric capacitor.

An integrated circuit comprising:

• a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode;
• a latch circuit, connected to said second power line, which is constituted by a transistor of a second threshold voltage which is lower than said first threshold voltage;
• a combinational circuit, connected to said second power line, which is constituted by a transistor of said second threshold voltage;
• a nonvolatile data holding circuit for storing data held by said latch circuit during said sleep mode;
• and
• a control signal generating circuit which, when returning to an active mode from said sleep mode, generates a recall signal for generating a voltage in said latch circuit in accordance with the state of said nonvolatile data holding circuit, and thereafter generates a sleep signal for causing said sleep switch to conduct to thereby activate said latch circuit.