US 7,080,179 B1 · Multi-level interrupts

Abstract

Multiple levels of interrupts to be utilized in a computer system, which allows, for example, an interrupt with an interrupt level associated with an application to be distinct from an interrupt with an interrupt level associated with a kernel. The kernel level interrupt may be handled quickly via its own handler, while the application level interrupt may be handled more slowly. This may be accomplished by first determining if a first-level handler is installed for the interrupt source. If so, then it may be called. Otherwise, the interrupt source may be masked and a second-level handler may be called. Once this second-level handler has completed its tasks, the interrupt source may then be unmasked. Implementations with three or more levels of interrupt are also possible.

Claims34

Dependent claims

A method for handling an interrupt in a computer system, the interrupt having a source, the method comprising:

determining if a first-level handler is installed for the interrupt source;
calling said first-level handler if one is installed for the interrupt source;
masking the interrupt source if a first-level handler is not installed for the interrupt source;
calling a second-level handler if a first-level handler is not installed for the interrupt source;
and
unmasking the interrupt source if a first-level handler is not installed for the interrupt source.

3 more elements

Dependencies are inferred from the claim text.

Multi-level interrupts

Life of this patent

Multi-level interrupts

Life of this patent

Abstract

Claims34