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AssigneeBroadcom Corporation
InventorsKeshab K Parhi, Jin-Gyun Chung, Sang-Min Kim
Estimating the term…
An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.
A fixed-width multiplier, comprising:
An integrated circuit having a substrate and a fixed-width multiplier disposed on said substrate, said fixed-width multiplier being designed by:
A method for forming an error compensation bias circuit for a fixed-width multiplier, the method comprising:
An error compensation bias circuit for a fixed-width multiplier having a plurality of adder cells, comprising:
Dependencies are inferred from the claim text.