Noise suppression in memory device sensing

A method of writing to a target memory cell, comprising:

• applying a first potential to first variable-potential nodes associated with switching a first latch;
• switching the first latch to a state indicative of a data value to be written to the target memory cell while the first variable-potential nodes have their first potential;
• applying a second potential to the first variable-potential nodes while holding the first latch in its state indicative of the data value;
• applying a first potential to second variable-potential nodes associated with switching a second latch;
• switching the second latch to a state indicative of the state of the first latch and of the data value while the second variable-potential nodes have their first potential and while the first variable-potential nodes have their second potential;
• applying a second potential to the second variable-potential nodes while holding the second latch in its state indicative of the data value;
• and
• coupling the second latch to a bit line coupled to the target memory cell while applying the second potential to the second variable-potential nodes.

A method of passing data between latches in a sensing device of a memory device, the method comprising:

• applying a first potential to first nodes associated with switching a first latch of the sensing device during a switching period of the first latch;
• applying a second potential to the first nodes during a holding period of the first latch, wherein the second potential of the first nodes is greater than the first potential of the first nodes and less than a supply potential;
• and
• passing a state of the first latch to a second latch of the sensing device during the holding period of the first latch.

A sensing device, comprising:

• a first latch for providing a first signal at a first node of the first latch and having a logic level indicative of a data value of a target memory cell, wherein the first latch is selectively coupled to one or more first variable-potential nodes for switching the first latch;
• and
• a second latch for providing a second signal at a first node of the second latch and having a logic level indicative of the data value, wherein the second latch is selectively coupled to one or more second variable-potential nodes for switching the second latch;
• a first ground control circuit coupled to receive a first control signal and to provide a variable potential to the first variable-potential nodes responsive to the first control signal;
• and
• a second ground control circuit coupled to receive a second control signal and to provide a variable potential to the second variable-potential nodes responsive to the second control signal.

A memory device, comprising:

• an array of memory cells;
• and
• a sensing device for sensing a data value of a target memory cell of the array of memory cells, the sensing device comprising:
• a first latch for providing a first signal at a first node of the first latch and having a logic level indicative of the data value of the target memory cell, wherein the first latch is selectively coupled to one or more first variable-potential nodes for switching the first latch;
• and
• a second latch for providing a second signal at a first node of the second latch and having a logic level indicative of the data value, wherein the second latch is selectively coupled to one or more second variable-potential nodes for switching the second latch;
• a first ground control circuit coupled to receive a first control signal and to provide a variable potential to the first variable-potential nodes responsive to the first control signal;
• and
• a second ground control circuit coupled to receive a second control signal and to provide a variable potential to the second variable-potential nodes responsive to the second control signal;
• wherein the first ground control circuit and the second ground control circuit are adapted to provide either a ground potential or an intermediate potential greater than the ground potential and less than a supply potential;
• and
• wherein the first ground control circuit and the second ground control circuit are further adapted to provide their ground potentials or intermediate potentials independently of each other.

An electronic device, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device comprises:
• an array of memory cells;
• and
• a sensing device for sensing a data value of a target memory cell of the array of memory cells, the sensing device comprising:
• a first latch for providing a first signal at a first node of the first latch and having a logic level indicative of the data value of the target memory cell, wherein the first latch is selectively coupled to one or more first variable-potential nodes for switching the first latch;
• and
• a second latch for providing a second signal at a first node of the second latch and having a logic level indicative of the data value, wherein the second latch is selectively coupled to one or more second variable-potential nodes for switching the second latch;
• a first ground control circuit coupled to receive a first control signal and to provide a variable potential to the first variable-potential nodes responsive to the first control signal;
• and
• a second ground control circuit coupled to receive a second control signal and to provide a variable potential to the second variable-potential nodes responsive to the second control signal;
• wherein the first ground control circuit and the second ground control circuit are adapted to provide either a ground potential or an intermediate potential approximately one Vt less than a supply potential;
• and
• wherein the first ground control circuit and the second ground control circuit are further adapted to provide their ground potentials or intermediate potentials independently of each other.