Wafer level burn-in of SRAM
AssigneeUnited Microelectronics Corp.
InventorsChih-Hung Chen, Te-Sun Wu
Life of this patent
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Abstract
A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.
Claims20
A wafer level burn-in for static random access memory, wherein the static random access memory has a plurality of word lines, a plurality of bit lines and a plurality of pull-up circuits and equalizer circuits connected to the bit lines, the burn-in test comprising:
- switching on all word lines of the static random access memory;
- shutting down all the pull-up circuits and the equalizer circuits;
- setting a high voltage at one bit line of every bit line pair and setting a low voltage at another bit line of every bit line pair;
- and
- determining normality of a static random access memory according to an eventual current at an end of a first steady state.
A wafer level burn-in method for a static random access memory having a plurality of parallel master word lines, a plurality of local word lines, a plurality of conductive lines Vcc and a plurality of conductive lines Vss all on a same layer as well as a plurality of bit lines on another layer, wherein the master word lines, the local word lines, the conductive lines Vcc and the conductive lines Vss are arranged in a specified sequence, and moreover, the bit lines are connected to a plurality of pull-up circuits and a plurality of equalizer circuits, wherein the wafer level burn-in method includes:
- shutting all the pull-up circuits and the equalizer circuits;
- applying a high voltage to a bit line of every bit line pair and applying a low voltage to another bit line of the bit line pair;
- applying a high voltage and a low voltage between any neighboring combinations of the master word lines, the local word lines, the conductive lines Vcc and the conductive lines Vss;
- and
- determining normality of a static random access memory according to an eventual current at an end of a first steady state.
Dependencies are inferred from the claim text.