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US 7,079,419 B2Granted
NAND flash memory with read and verification for threshold uniformity
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground potential in the flash memory device. A first word line signal is coupled to the first accessed cell. The first word line signal voltage level is adjusted in response to the position of the first accessed cell in its series of cells.
Claims22
A flash memory device comprising:
- a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference;
- and
- controller circuitry, coupled to the memory array, for controlling operation of the device, the controller circuitry adapted to execute a method for increasing read and erase verification threshold uniformity comprising determining a position, with reference to a ground potential, of a first accessed cell in the series configuration and adjusting a first word line signal voltage level, coupled to the first accessed cell, in response to the position of the first accessed cell.
A NAND flash memory device comprising:
- a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference;
- and
- control circuitry, coupled to the memory array, the control circuitry adapted to execute methods for controlling operation of the memory device including determining a position, with reference to a ground potential, of a first accessed cell of the plurality of memory cells, generating a word line signal having a first voltage level in response to an address input, and compensating the first voltage level in response to the position of the first accessed cell.
An electronic system comprising:
- a processor that generates memory signals;
- and
- a flash memory device, coupled to the processor, that operates in response to the memory signals, the device comprising:
- a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference;
- a column decoder that generates the bit line;
- a row decoder that generates a word line having a nominal voltage level;
- and
- a voltage generator circuit, coupled between the row decoder and the memory array, that adjusts the nominal voltage level in response to the position of a first memory cell indicated by the word line.
5 more elements
A NAND flash memory device comprising:
- a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference;
- and
- control circuitry, coupled to the memory array, the control circuitry adapted to execute a method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising reading a first cell of the plurality of cells, determining a position of the first cell with reference to a ground potential in the flash memory device, and generating a reference current in response to the position.
A NAND flash memory device comprising:
- a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference;
- and
- control circuitry, coupled to the memory array, the control circuitry adapted to execute a method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising reading a first cell of the plurality of cells, determining a position of the first cell with reference to a ground potential in the flash memory device, and generating one of a reference current or voltage in response to the position.
An electronic system comprising:
- a controller circuit that generates memory signals;
- and
- a flash memory device, coupled to the controller circuit, that operates in response to the memory signals, the device comprising:
- a memory array comprising a plurality of cells coupled together in a plurality of series configurations;
- and
- a reference generator that generates a measurement reference for each of the plurality of cells based on their locations in each of the plurality of series configurations.
3 more elements
Dependencies are inferred from the claim text.