Programmable MOS device formed by stressing polycrystalline silicon

A method for programming a metal-oxide-semiconductor (MOS) memory circuit, the circuit comprising a data read module having a first input and a second input and one or more outputs, a first and second polycrystalline resistors having their first ends connectable to a first control voltage level and their second end connected to a second voltage level, and a connection module for connecting the first ends of the first and second resistors to the first and second inputs respectively, the method comprising:

• disenabling the connection module for disconnecting the first ends of the resistors from the first and second inputs;
• imposing the first control voltage on the first end of the first or second resistor;
• and
• relieving the first control voltage from the connected first end of either the first or second resistor.

A programmable metal-oxide-semiconductor (MOS) memory circuit comprising:

• a first polycrystalline resistor having a first end connectable to a first control voltage level, and a second end connectable to a second voltage level;
• and
• a second polycrystalline resistor having a first end connectable to the first control voltage level, and a second end connectable to the second voltage level.
• wherein the first and second control voltage levels are imposed to program either the first or second resistor by causing a current stress across the resistor that causes hot carrier effects for programming the memory circuit.

A polycrystalline silicon resistor pair used in a programmable memory cell comprising:

• a first polycrystalline silicon resistor stressable by a predetermined current thereacross;
• a second polycrystalline silicon resistor similarly structured as the first polycrystalline silicon resistor stressable by the predetermined current;
• and
• means for reading the programmed memory cell, including a first output and a second output based on a voltage difference between a first input and a second input wherein the first and second inputs are connectable to first ends of the first and second resistors to generate the first and second outputs of the latch representing a programmed value of the memory cell,
• wherein when only the first resistor is stressed by the predetermined current, a resistance of the first resistor is lowered as compared to the unstressed second resistor, thereby programming the memory cell.