System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal

A system for generating an output clock signal that has a predetermined phase relative to a periodic input clock signal, comprising:

• a measurement delay line including a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a first input signal to a final delay circuit, the first input signal having transitions corresponding to predetermined transitions of the input clock signal, the delay circuits propagating the first input signal through the delay circuits from the initial delay circuit toward the final delay circuit;
• a plurality of latches coupled to the measurement delay line, the latches being set by the measurement delay line to provide an indication of the number of delay circuits in the measurement delay line through which a transition of the first input signal has propagated when a subsequent transition of the first input signal is received by the measurement delay line;
• a signal generating delay line having a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a second input signal to a final delay circuit, the number of delay circuits in the signal generating delay line being a sub-multiple of the number of delay circuits in the measurement delay line, the operation of the signal generating delay line being controlled by the latches so that the percentage of delay circuits in the signal generating delay line through which the second input signal propagates to generate the output clock signal is substantially the same as the percentage of delay circuits in the measurement delay line through which the first input signal propagates when a subsequent transition of the first input signal is received by the measurement delay line;
• and
• a control circuit that is operable to disable the first input signal from propagating through the measurement delay line for a disable period.

A clock multiplier system for generating an output clock signal having a frequency that is a predetermined multiple of the frequency of a periodic input clock signal, the system comprising:

• a measurement delay line including a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a first input signal to a final delay circuit, the first input signal having transitions corresponding to predetermined transitions of the input clock signal, the delay circuits propagating the first input signal through the delay circuits from the initial delay circuit toward the final delay circuit;
• a plurality of latches coupled to the measurement delay line, the latches being set by the measurement delay line to provide an indication of the number of delay circuits in the measurement delay line through which a transition of the first input signal has propagated when a subsequent transition of the first input signal is received by the measurement delay line;
• a plurality of signal generating delay lines each having a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a respective input signal to a final delay circuit, the number of delay circuits in each of the signal generating delay lines being a sub-multiple of the number of delay circuits in the measurement delay line, the operation of the signal generating delay lines being controlled by the latches so that the percentage of delay circuits in the signal generating delay line through which the second input signal propagates to generate respective output clock signals is substantially the same as the percentage of delay circuits in the measurement delay line through which the first input signal propagates when a subsequent transition of the first input signal is received by the measurement delay line, the output clock signals having phases relative to the second input signal that are different from each other;
• a control circuit that is operable to disable the first input signal from propagating through the measurement delay line for a disable period;
• and
• a logic circuit coupled to receive the output clock signals from the signal generating delay lines, the logic circuit being operable to combine the output clock signals from the signal generating delay lines to generate the output clock signal.

A system for correcting the duty cycle of an input clock signal, comprising:

• a measurement delay line including a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a first input signal to a final delay circuit, the first input signal having transitions corresponding to predetermined transitions of the input clock signal, the delay circuits propagating the first input signal through the delay circuits from the initial delay circuit toward the final delay circuit;
• a plurality of latches coupled to the measurement delay line, the latches being set by the measurement delay line to provide an indication of the number of delay circuits in the measurement delay line through which a transition of the first input signal has propagated when a subsequent transition of the first input signal is received by the measurement delay line;
• first and second signal generating delay lines each having a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a respective input signal to a final delay circuit, the number of delay circuits in each of the first and second signal generating delay lines being a sub-multiple of the number of delay circuits in the measurement delay line, the operation of the signal generating delay lines being controlled by the latches so that the percentage of delay circuits in the signal generating delay line through which the second input signal propagates to generate respective output clock signals is substantially the same as the percentage of delay circuits in the measurement delay line through which the first input signal propagates when a subsequent transition of the first input signal is received by the measurement delay line, the output clock signals having phases that are the compliment of each other;
• a control circuit that is operable to disable the first input signal from propagating through the measurement delay line for a disable period;
• and
• a duty cycle correcting circuit, comprising a flip-flop having set and reset inputs, one of the set and reset inputs being coupled to receive the output clock signal from the first signal generating delay line and the other of the set and reset inputs being coupled to receive the output clock signal from the second signal generating delay line, the flip-flop having an output from which a duty cycle corrected clock signal is generated.

A memory device, comprising:

• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• a memory cell array operable to store data written to the array at a location determined by the decoded row address signals and the decoded column address signals;
• a read data path circuit operable to couple read data signals from each of the arrays to external data terminals of the memory device;
• a write data path circuit operable to couple write data signals from the external data terminals of the memory device and to couple the write data signals to one of the arrays;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• and
• a signal generator operable to generate either the write data strobe signal or the read data strobe signal, the signal generator comprising:
• a system for generating an output clock signal that has a predetermined phase relative to a periodic input clock signal, comprising:
• a measurement delay line including a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a first input signal to a final delay circuit, the first input signal having transitions corresponding to predetermined transitions of an input clock signal, the delay circuits propagating the first input signal through the delay circuits from the initial delay circuit toward the final delay circuit;
• a plurality of latches coupled to the measurement delay line, the latches being set by the measurement delay line to provide an indication of the number of delay circuits in the measurement delay line through which a transition of the first input signal has propagated when a subsequent transition of the first input signal is received by the measurement delay line;
• a signal generating delay line having a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a second input signal to a final delay circuit, the number of delay circuits in the signal generating delay line being a sub-multiple of the number of delay circuits in the measurement delay line, the operation of the signal generating delay line being controlled by the latches so that the percentage of delay circuits in the signal generating delay line through which the second input signal propagates to generate the strobe signal is substantially the same as the percentage of delay circuits in the measurement delay line through which the first input signal propagates when a subsequent transition of the first input signal is received by the measurement delay line;
• and
• a control circuit that is operable to disable the first input signal from propagating through the measurement delay line for a disable period.

A computer system, comprising

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising:
• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• and
• a memory device, comprising:
• a memory cell array operable to store data written to the array at a location determined by the decoded row address signals and the decoded column address signals;
• a read data path circuit operable to couple read data signals from each of the arrays to external data terminals of the memory device;
• a write data path circuit operable to couple write data signals from the external data terminals of the memory device and to couple the write data signals to one of the arrays;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• and
• a signal generator operable to generate either the write data strobe signal or the read data strobe signal, the signal generator comprising:
• a measurement delay line including a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a first input signal to a final delay circuit, the first input signal having transitions corresponding to predetermined transitions of an input clock signal, the delay circuits propagating the first input signal through the delay circuits from the initial delay circuit toward the final delay circuit;
• a plurality of latches coupled to the measurement delay line, the latches being set by the measurement delay line to provide an indication of the number of delay circuits in the measurement delay line through which a transition of the first input signal has propagated when a subsequent transition of the first input signal is received by the measurement delay line;
• a signal generating delay line having a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a second input signal to a final delay circuit, the number of delay circuits in the signal generating delay line being a sub-multiple of the number of delay circuits in the measurement delay line, the operation of the signal generating delay line being controlled by the latches so that the percentage of delay circuits in the signal generating delay line through which the second input signal propagates to generate the strobe signal is substantially the same as the percentage of delay circuits in the measurement delay line through which the first input signal propagates when a subsequent transition of the first input signal is received by the measurement delay line;
• and
• a control circuit that is operable to disable the first input signal from propagating through the measurement delay line for a disable period.

A method of generating an output clock signal having a predetermined phase relative to an input clock signal, comprising:

• applying a first input signal corresponding to the input clock signal to a first of a first plurality of delay elements connected in series with each other;
• determining the percentage of the delay elements in the first plurality through which the first input signal has propagated after a delay corresponding to the period of the input clock signal;
• saving the result of the percentage determination;
• allowing a second input signal to propagate through at least some of a second plurality of delay elements connected in series with each other, the number of delay elements in the second plurality being a sub-multiple of the number of delay elements in the first plurality, the percentage of delay elements in the second plurality through which the second input signal propagates to generate the output clock signal being controlled during each of a predetermined plurality of periods of the second input signal by the saved percentage determination result so that the percentage of delay elements in the second plurality through which the second input signal propagates is substantially equal to the percentage of the delay elements in the first plurality the first input signal has propagated.

A method of generating an output clock signal having a selected phase shift relative to an input clock signal, comprising:

• allowing the input clocks signal to propagate through a plurality of delay elements in a measurement delay line;
• setting a latch corresponding to the number of delay elements in the measurement delay line through which the input clock signal has propagated by the next transition of the input clock signal;
• and
• using the set latch to determine the number of delay elements in a signal generating delay line through which a signal propagates to generate a respective output signal, the number of delay elements in the signal generating delay line being a sub-multiple of the number of delay elements in the measurement delay line.

A method of generating an output clock signal having a selected phase shift relative to an input clock signal, comprising:

• allowing the input clock signal to propagate through a plurality of delay elements in a measurement delay line;
• setting a latch corresponding to the number of delay elements in the measurement delay line through which the input clock signal has propagated by the next transition of the input clock signal;
• and
• using the set latch to determine the number of delay elements in a signal generating delay line through which a signal propagates to generate a respective output signal;
• allowing the latch to remain set for a plurality of cycles of the input clock signal;
• and
• preventing the input clock signal from propagating through the measurement delay line during each of the plurality of cycles of the input clock signal.