Analog delay locked loop having duty cycle correction circuit

An analog delay locked loop device comprising:

• a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs;
• and
• a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs,
• wherein the first block includes:
• a reference delay line which receives the internal clock signal to output the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs;
• and
• a reference control means which forms a reference loop with the reference delay line and controls the reference delay line for the reference clock signal and one signal of last clock signal pair of the normal multi clock signal pairs to have an opposite phase.