Methodology to accurately test clock to signal valid and slew rates of PCI signals
AssigneeLSI Logic Corporation
InventorsKeith Grimes, Raymond S. Rowhuff, William Schmitz
Life of this patent
Estimating the term…
Abstract
A method for populating and depopulating components of negligible impedance facilitates the testing of circuit boards. The test circuitry may be formed upon the circuit board under test. Testing may be performed with great accuracy for the time between the triggering edge of a clock pulse and a resulting valid signal change. Slew rates of bus signals may be more easily measured.
Claims5
A method for configuring a bus driver circuit for testing, comprising the steps of:
- providing a connectable first path at or near a bus driver output for a normal, operational mode on a circuit board;
- providing a connectable second path at or near the bus driver output for a test mode performed by a test circuit on the circuit board;
- and
- physically installing a bridging component of negligible impedance at one of the connectable first and second paths,
- wherein the bridging component of negligible impedance is a zero ohm resistor.
A system for measuring the rise and fall times of a bus driver signal, comprising:
- a circuit board having a bus driver circuit for generating a bus driver signal and a test circuit capable of being coupled to the bus driver circuit, the test circuit having a test point, the bus driver signal propagating through one of a first connectable path for a normal, operational mode and a second connectable path to the test circuit for a test mode;
- and
- a measuring device having a probe that makes electrical contact with the test point of the test circuit,
- wherein one of the first and second connectable paths is connected by the physical installation of a component of negligible impedance, and
- wherein the component of negligible impedance is a zero ohm resistor.
A system for measuring the rise and fall times of a bus driver signal, comprising:
- a circuit board having a bus driver circuit for generating a bus driver signal and a test circuit capable of being coupled to the bus driver circuit, the test circuit having a test point, the bus driver signal propagating through one of a first connectable path for a normal, operational mode and a second connectable path to the test circuit for a test mode;
- and
- a measuring device having a probe that makes electrical contact with the test point of the test circuit,
- wherein one of the first and second connectable paths is connected by the physical installation of a component of negligible impedance, and
- wherein the rise time of the driver bus signal is measured in the test circuit in which the test circuit has a pull down resistor and a capacitor.
A system for measuring the rise and fall times of a bus driver signal, comprising:
- a circuit board having a bus driver circuit for generating a bus driver signal and a test circuit capable of being coupled to the bus driver circuit, the test circuit having a test point, the bus driver signal propagating through one of a first connectable path for a normal, operational mode and a second connectable path to the test circuit for a test mode;
- and
- a measuring device having a probe that makes electrical contact with the test point of the test circuit,
- wherein one of the first and second connectable paths is connected by the physical installation of a component of negligible impedance, and
- wherein the fall time of the driver bus signal is measured in the test circuit in which the test circuit has a pull up resistor and a capacitor.
Dependencies are inferred from the claim text.