Fully depleted silicon-on-insulator CMOS logic

A vertical multiple bit memory cell having a silicon-on-insulator structure on a substrate, the memory cell comprising:

• a vertical metal oxide semiconductor field effect transistor (MOSFET) extending horizontally outward from a substrate, the MOSFET having a drain region, a source region, a channel region between the source and drain regions, and a gate separated from the channel region by a high dielectric constant gate insulator that can store a first charge in a first storage region and a second charge in a second storage region;
• a first transmission line coupled to the drain region;
• a second transmission line coupled to the source region;
• and
• an extractor contact coupled to the channel region in the silicon-on-insulator such that a reverse bias voltage on the extractor contact fully depletes the channel region.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device includes a memory array having a plurality of memory cells with a silicon-on-insulator structure, each memory cell comprising:
• a drain region comprising a first doped material and formed in the silicon-on-insulator;
• a source region comprising the first doped material and formed in the silicon-on-insulator;
• a control gate formed above and substantially between the drain and source regions;
• and
• an extractor contact comprising a second doped material and coupled to a depletion region in the silicon-on-insulator substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact.

A silicon-on-insulator inverter comprising:

• a PMOS transistor formed in an n+ well in an insulator structure on a substrate, the transistor comprising:
• a drain region comprising a first p+ doped region in the n+ well;
• a source region comprising a second p+ doped region in the n+ well;
• an control gate formed above and substantially between the drain and source regions;
• and
• an extractor contact coupled to a depletion region in the n+ well substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact;
• and
• an NMOS transistor coupled to the PMOS transistor and formed in a p+ well in the insulator structure on the substrate, the transistor comprising:
• a drain region comprising a first n+ doped region in the p+ well, the drain region coupled to the NMOS source region;
• a source region comprising a second n+ doped region in the p+ well;
• a control gate formed above and substantially between the drain and source regions, the PMOS control gate coupled to the NMOS control gate;
• and
• an extractor contact coupled to a depletion region in the p+ well substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact.