Dual layer patterning scheme to make dual damascene
AssigneeAdvanced Micro Devices, Inc.
InventorsBhanwar Singh, Ramkumar Subramanian, Bharath Rangarajan, Michael K. Templeton
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AssigneeAdvanced Micro Devices, Inc.
InventorsBhanwar Singh, Ramkumar Subramanian, Bharath Rangarajan, Michael K. Templeton
Estimating the term…
One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
A method for making a dual damascene pattern in a single etch process comprising:
A method for making a dual damascene pattern using a dual layer patterning scheme and a single etch process comprising:
A method for making a dual damascene pattern using a dual layer patterning scheme comprising:
Dependencies are inferred from the claim text.