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US 7,078,303 B2Granted
Method for manufacturing semiconductor device having thick insulating layer under gate side walls
AssigneeOki Electric Industry Co., Ltd.
InventorsMasahiro Yoshida, Shunichi Tokitoh
Life of this patent
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Abstract
A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.
Claims20
A method of manufacturing a semiconductor device comprising:
- preparing a semiconductor substrate;
- forming a gate insulating layer on the semiconductor substrate;
- forming a gate electrode layer on the gate insulating layer;
- patterning the gate electrode layer to form a gate electrode pattern;
- forming an LDD region on the semiconductor substrate;
- depositing an oxide layer on the semiconductor substrate, wherein a thickness of the oxide layer is greater than a thickness of the gate insulating layer;
- forming a nitride layer on the oxide layer;
- and
- etching the oxide layer and the nitride layer to form a nitride sidewall spacer on a gate electrode through the oxide layer, wherein a final gate electrode structure includes a lower gate electrode layer and a top gate electrode layer, and wherein a height of the nitride sidewall spacer is substantially equal to or less than a total thickness of the gate electrode structure and more than a thickness of the lower gate electrode layer.
6 more elements
A method of manufacturing a semiconductor device comprising:
- preparing a semiconductor substrate;
- oxidizing the semiconductor substrate to form a gate insulating layer on the semiconductor substrate;
- forming a polysilicon layer on the gate insulating layer;
- patterning the polysilicon layer to form a gate electrode pattern;
- forming an LDD region on the semiconductor substrate using the gate electrode pattern as a mask;
- depositing an oxide layer on the semiconductor substrate, wherein a thickness of the oxide layer is greater than a thickness of the gate insulating layer;
- forming a nitride layer on the oxide layer;
- and
- etching the oxide layer and the nitride layer to form a nitride sidewall spacer on the gate electrode pattern, wherein a final gate electrode structure includes the gate electrode pattern and a top gate electrode, and wherein a height of the nitride sidewall spacer is substantially equal to or less than a total thickness of the gate electrode structure and more than a thickness of the gate electrode pattern.
6 more elements
A method of manufacturing a MOSFET comprising:
- preparing a semiconductor substrate;
- forming a gate insulating layer on the semiconductor substrate;
- forming a gate electrode layer on the gate insulating layer;
- removing a part of the gate electrode layer to form a gate electrode pattern;
- implanting ions into the semiconductor substrate using the gate electrode pattern as a mask to form an LDD region on the semiconductor substrate;
- depositing an oxide layer on the semiconductor substrate by a CVD, wherein a thickness of the oxide layer is greater than a thickness of the gate insulating layer;
- forming a nitride layer on the oxide layer;
- and
- subjecting the oxide layer and the nitride layer to anisotropic etching to form a nitride sidewall spacer on a gate electrode, wherein a final gate electrode structure includes the gate electrode pattern and a top gate electrode, and wherein a height of the nitride sidewall spacer is substantially equal to or less than a total thickness of the gate electrode structure and more than a thickness of the gate electrode pattern.
6 more elements
Dependencies are inferred from the claim text.