US 7,073,086 B2 · System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit

Abstract

The clock signal is the dominant source of electromagnetic interference (EMI) for many electronic devices. EMI generated by an electronic device must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. EMI emissions are reduced by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. Implementations of the tunable delay lines are provided. In one implementation, a tunable delay line includes a first pipeline, a second pipeline, and a coupling mechanism for coupling the first pipeline to the second pipeline at various transfer points. The forward latency of the second pipeline is longer than that of the first pipeline. Based on external control signals, a clock pulse traveling along the first pipeline can be transferred via the coupling mechanism to the second pipeline thereby allowing the clock pulse to continue to propagate along the second pipeline.

Claims24

Dependent claims

A circuit for controlling signal propagation, comprising:

a first signal-propagating pipeline having a first adjustable forward latency;
a second signal-propagating pipeline having a second adjustable forward latency;
and
a plurality of transfer points from a first plurality of points along the first signal-propagating pipeline to a second plurality of points along the second signal-propagating pipeline for allowing a signal propagating along the first signal-propagating pipeline to be transferred to the second signal-propagating pipeline via one of the plurality of transfer points;
wherein the first adjustable forward latency is longer than the second adjustable forward latency.

2 more elements

A signal propagation control circuit, comprising:

a first plurality of propagation stages sequentially coupled to one another, the first plurality of propagation stages collectively having a first adjustable forward latency;
a second plurality of propagation stages sequentially coupled to one another, the second plurality of propagation stages collectively having a second adjustable forward latency;
and
a plurality of coupling stages for coupling the first plurality of propagation stages to the second plurality of propagation stages;
wherein each stage of the first plurality of propagation stages is coupled to a corresponding stage of the second plurality of propagation stages via a corresponding coupling stage, wherein a first stage of the first plurality of propagation stages is coupled to a corresponding first stage of the second plurality of propagation stages and a second stage of the first plurality of propagation stages is coupled to a corresponding second stage of the second plurality of propagation stages;
wherein a signal propagating along the first plurality of propagation stages is capable of being transferred to the second plurality of propagation stages via one of the plurality of coupling stages in response to a control signal, thereby allowing the signal to propagate along the second plurality of propagation stages;
and
wherein the first adjustable forward latency is longer than the second adjustable forward latency.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/306,721Filed 27 Nov 2002 · us provisional application

Priority

27 Nov 2001

Published

US 2003/0177409 A118 Sep 2003

Granted

4 Jul 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/3869
Using instruction pipelines: implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
H03K 5/133
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: using a chain of active delay…
H03K 2005/00019
Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse: variable delay
H03K 2005/00234
Layout of the delay element: using circuits having two logic levels

System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit

Life of this patent

System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit

Life of this patent

Abstract

Claims24