US 7,072,922 B2 · Integrated circuit and process for identifying minimum or maximum input value among plural inputs

Abstract

Apparatus and process identifies a maximum or minimum value among a plurality of binary values on a plurality of a-bit wide wires in an integrated circuit module. An N-bit vector K is calculated based on n most significant bits of all a-bit binary signals, where N=2n. M N-bit vectors K—0, . . . ,K_(M−1) are calculated based on the n most significant and the m least significant bits of all a-bit binary signals, where M is at least 2m−1. A table is constructed from vectors K—0, . . . ,K(M−1) to create table vectors. A table vector is selected based on vector K, is used to derive a vector P, which in turn is used to select another table vector. The minimum or maximum binary value is identified from the two selected table vectors.

Claims20

Dependent claims

Apparatus for identifying a maximum or minimum value among a plurality of values represented by respective a-bit binary signals on a plurality of a-bit wide wires in an integrated circuit module, the apparatus comprising:

first means responsive to the a-bit binary signal on each of the plurality of wires to calculate an N-bit vector K based on n most significant bits of all a-bit binary signals and to calculate M N-bit vectors K_0, . . . ,K_(M−1) based on the n most significant bits and m least significant bits of all a-bit binary signals, where n=a−m, N=2n, M is at least 2m−1 and m is either a/2 or (a−1)/2;
second means responsive to vectors K_0, . . . ,K(M−1) for calculating N table vectors;
third means responsive to vector K for selecting one of the table vectors to derive a vector P;
fourth means responsive to vector P for selecting a table vector;
and
an output for calculating the minimum or maximum binary value from the vectors selected by the third and fourth means.

3 more elements

A process of identifying a maximum or minimum binary value among a plurality of values represented by respective a-bit binary signals on a plurality of a-bit wide wires in an integrated circuit module, the process comprising steps of:

a) calculating an N-bit vector K based on n most significant bits of all a-bit binary signals, where n=a−m, N=2n and m is either a/2 or (a−1)/2;
b) calculating M N-bit vectors K_0, . . . ,K_(M−1) based on the n most significant and the m least significant bits of all a-bit binary signals, where M is at least 2m−1;
c) calculating N table vectors based on vectors K_0, . . . ,K(M−1);
d) selecting one of the table vectors based on vector K;
e) selecting a table vector based on a vector P derived from the table vector selected in step d);
and
f) identifying the minimum or maximum binary value among the plurality of values represented by the respective a-bit binary signals on the plurality of a-bit wide wires based on the vectors selected in steps d) and e).

4 more elements

Dependencies are inferred from the claim text.

Integrated circuit and process for identifying minimum or maximum input value among plural inputs

Life of this patent

Integrated circuit and process for identifying minimum or maximum input value among plural inputs

Life of this patent

Abstract

Claims20