Clamping and de-clamping semiconductor wafers on a J-R electrostatic chuck having a micromachined surface by using force delay in applying a single-phase square wave AC clamping voltage

Abstract

The present invention is directed to a method and a system for clamping a wafer to a J-R electrostatic chuck using a single-phase square wave AC clamping voltage. The method comprises determining a single-phase square wave clamping voltage for the J-R electrostatic chuck, wherein the determination is based, at least in part, on a minimum residual clamping force associated with the wafer and the electrostatic chuck and a surface topography of a leaky dielectric layer associated therewith. The wafer is placed on the electrostatic chuck; and the determined clamping voltage is applied to the electrostatic chuck, therein electrostatically clamping the wafer to the electrostatic chuck, wherein at least the minimum residual clamping force is maintained during a polarity switch of the single-phase square wave clamping voltage. The determination of the surface topography comprises a first gap and a second gap between the wafer and the electrostatic chuck and an island area ratio, wherein a difference in RC time constants associated with the respective first gap and second gap is provided such that at least the minimum residual clamping force is maintained during the polarity switch. Upon removal of the square wave clamping voltage, the de-clamping time is substantially reduced, and corresponds to the pulse width of the square wave clamping voltage.

Dependencies are inferred from the claim text.