Back-drive circuit protection for I/O cells using CMOS process
AssigneeNational Semiconductor Corporation
InventorKhusrow Kiani
Life of this patent
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Abstract
In a high tolerance I/O interface with over-voltage protection beyond 5 V, a cascoded driver with PMOS pull-up and NMOS pull-down transistors, connected to a pad, is provided. Circuitry is included to maintain the floating well voltages of the PMOS pull-up driver transistors at substantially the same voltages as their respective drains, and their gate voltages at substantially the same voltages as their respective drains, under back-drive and 5 V tolerant mode. Circuitry is also provided to increase the gate voltage of one of a cascoded pair of NMOS pull-down driver transistors, so that the drain-source junction voltage and gate oxide voltage of the transistor will be less than the breakdown voltage under back-drive and 5 V tolerant mode.
Claims15
A cascoded driver circuit having two PMOS transistors and two NMOS transistors, the transistors each having a drain, a source, a gate, and a well, that includes circuitry for charging the gates and wells of the cascoded PMOS transistors of the driver circuit to the same voltages as the respective drains of the cascaded PMOS transistors.
A driver circuit comprising
- a first PMOS transistor connected to a pad,
- a second PMOS transistor connected with its drain to the source of the first PMOS transistor,
- a first NMOS transistor with its drain connected to the pad, and
- a second NMOS transistor with its drain connected to the source of the first NMOS transistor, wherein
- means for charging the gate of the first PMOS transistor to substantially the same voltage as the pad,
- means for charging the well of the first PMOS transistor to substantially the same voltage as the pad,
- means for charging the drain of the second PMOS transistor is to a voltage that avoids drain-source junction breakdown of the second PMOS transistor, and
- means for charging the gate and well of the second PMOS transistor to substantially the same voltage as the voltage of the drain of the second PMOS transistor.
A method of enhancing the tolerance of a drive circuit during stress mode, comprising
- providing a cascoded circuit of a first PMOS transistor connected to a pad, a second PMOS transistor, and first and second NMOS transistors,
- charging the gate of the first PMOS transistor to the pad voltage during stress mode, clamping the gate and drain of the second PMOS transistor to the same voltage, and
- switching off both PMOS transistors during stress mode.
Dependencies are inferred from the claim text.