Voltage level translator circuitry

A voltage translator, comprising:

• an output node;
• and
• circuitry that receives an input signal having a voltage potential, said circuitry operative to provide a HIGH voltage level and a LOW voltage level to said output node in response to the potential of said input signal, said circuitry comprising:
• a plurality of transistors that selectively couple said output node to said HIGH voltage level and said LOW voltage level;
• voltage protection circuitry coupled to a portion of said plurality of transistors that prevents voltage being applied to said portion from exceeding a predetermined source voltage level;
• a second output node that is selectively coupled to said HIGH voltage level and said LOW voltage level in response to an inverse of the potential of said input signal;
• first buffer circuitry coupled to said output node;
• and
• second buffer circuitry coupled to said second output node;
• wherein said first and second buffer circuitry are operative to selectively couple said HIGH voltage level and said LOW voltage level to utilization circuitry.

A method for translating a voltage using a voltage level translator operating at a predetermined source voltage level, said method comprising:

• receiving an input signal having a voltage potential;
• selectively coupling an output node to either a HIGH voltage level and a LOW voltage level in response to the potential of said input signal, said coupling being performed by a plurality of transistors;
• and
• preventing a difference in voltage across at least one of said plurality of transistors from exceeding a predetermined voltage level, wherein the difference in voltage across said at least one transistor is the difference between a first fixed source voltage level and a second fixed source voltage level.

A system comprising:

• a processor;
• a processor controller coupled to said processor;
• utilization circuitry coupled to said processor controller via voltage level translator circuitry, wherein said translator circuitry is operative to:
• receive an input signal having a voltage potential from said processor controller;
• selectively provide an output signal having either a HIGH voltage level or a LOW voltage level to said utilization circuitry in response to the potential of said input signal;
• and
• prevent a difference in voltage across at least a portion of said translator circuitry from exceeding a predetermined voltage level, wherein the difference in voltage across said portion is the difference between a first fixed source voltage level and a second fixed source voltage level.

An integrated circuit that is supplied with a predetermined source voltage level, comprising

• an output node;
• input circuitry that receives an input signal having a voltage potential;
• inverse input circuitry that receives an inverse of said input signal;
• translation circuitry coupled to said input circuitry, said inverse input circuitry, said output node, and a voltage source having a predetermined HIGH voltage level, wherein said input circuitry, said inverse input circuitry, and said translation circuitry are operative to selectively couple said output node to a ground voltage level and said predetermined HIGH voltage level;
• first voltage protection circuitry coupled to said input circuitry, said translation circuitry, and said predetermined source voltage level, and being operative to prevent the voltage being applied to a first portion of said translation circuitry and said input circuitry from exceeding said predetermined source voltage level;
• and
• second voltage protection circuitry coupled to said inverse input circuitry, said translation circuitry, and said predetermined source voltage level, and being operative to prevent the voltage being applied to a second portion of said translation circuitry and said inverse input circuitry from exceeding said predetermined source voltage level.

Voltage level translation circuitry, comprising:

• a first output node;
• a second output node;
• a cross-coupled circuitry coupled to a predetermined voltage level and to said first and second output nodes;
• first and second input circuitry that receive an input signal having a voltage potential ranging from a LOW voltage level to a HIGH voltage level, said first and second input circuitry operating in connection with said cross-coupled circuitry to selectively couple said first and second output nodes to said predetermined voltage level and said LOW voltage level;
• wherein said first input circuitry comprises:
• a first transistor having its drain coupled to said second output node, its gate connected to said predetermined voltage level, and its source coupled to a first connection node;
• a second transistor having its drain connected to said first connection node, its gate coupled to receive said input signal, and its source coupled to ground;
• and
• a third transistor having its source coupled to said predetermined voltage level, its gate coupled to receive said input signal, and its drain is coupled to said first connection node, said third transistor operative to maintain said first connection node at said predetermined voltage level when said input signal is at said LOW voltage level;
• and
• wherein said second input circuitry comprises:
• a fourth transistor having its drain coupled to said first output node, its gate connected to said predetermined voltage level, and its source coupled to a second connection node;
• a fifth transistor having its drain connected to said second connection node, its gate coupled to receive the inverse of said input signal, and its source coupled to ground;
• and
• an sixth transistor having its source coupled to said predetermined voltage level, its gate coupled to receive the inverse of said input signal, and its drain is coupled to said second connection node, said sixth transistor operative to maintain said second connection node at said predetermined voltage level when said input signal is at said HIGH voltage level.

An integrated circuit that is supplied with a predetermined source voltage level, comprising

• an output node;
• input circuitry that receives an input signal having a voltage potential;
• inverse input circuitry that receives an inverse of said input signal;
• translation circuitry coupled to said input circuitry, said inverse input circuitry, said output node, and a voltage source having a predetermined LOW voltage level, wherein said input circuitry, said inverse input circuitry, and said translation circuitry are operative to selectively couple said output node to a said predetermined source voltage level and said predetermined LOW voltage level;
• first voltage protection circuitry coupled to said input circuitry, said translation circuitry, and ground, and being operative to prevent the voltage being applied to a first portion of said translation circuitry and said input circuitry from exceeding said predetermined source voltage level;
• and
• second voltage protection circuitry coupled to said inverse input circuitry, said translation circuitry, and ground, and being operative to prevent the voltage being applied to a second portion of said translation circuitry and said inverse input circuitry from exceeding said predetermined source voltage level.

Voltage level translator circuitry, comprising:

• a first output node;
• a second output node;
• a cross-coupled circuitry coupled to a predetermined voltage level and to said first and second output nodes;
• first and second input circuitry that receive an input signal having a voltage potential ranging from a LOW voltage level to a HIGH voltage level, said first and second input circuitry operating in connection with said cross-coupled circuitry to selectively couple said first and second output nodes to said predetermined voltage level and said HIGH voltage level;
• wherein said first input circuitry comprises:
• a first transistor having its source coupled to a source voltage level, its gate coupled to receive said input signal, and its drain coupled to a first connection node;
• a second transistor having its source connected to said first connection node, its gate coupled to ground, and its drain coupled to said second output node;
• and
• a third transistor having its drain coupled to said first connection node, its gate coupled to receive said input signal, and its source coupled to ground, said third transistor operative to pull said first connection node to ground when said input signal is at said HIGH voltage level;
• and
• wherein said second input circuitry comprises:
• a fourth transistor having its source coupled to said source voltage level, its gate coupled to receive the inverse of said input signal level, and its drain coupled to a second connection node;
• a fifth transistor having its source connected to said second connection node, its gate coupled to ground, and its drain coupled to said first output node;
• and
• a sixth transistor having its drain coupled to said second connection node, its gate coupled to receive the inverse of said input signal, and its source coupled to ground, said third transistor operative to pull said second connection node to ground when said input signal is at said LOW voltage level.