US 7,071,076 B2 · Method of manufacturing semiconductor device

Abstract

A semiconductor device has an STI oxide film (106), of which surface is positioned higher than the surface of the silicon substrate (100) to prevent a pointed portion and a thin film thickness of a gate oxide film (108). The gate oxide film (106) becomes thicker toward a side wall (112) of the STI oxide film (106) to prevent the leakage current and increase the gate breakdown voltage.

Claims10

Dependent claims

A method of manufacturing a semiconductor device comprising the steps of:

scraping an upper surface of a silicon substrate by an anisotropic-etching such that an upper surface of an element-isolating region filled with an oxide film is positioned higher than said upper surface of said silicon substrate;
forming a sacrifice oxide film on said upper surface of said silicon substrate by oxidizing said upper surface of said silicon substrate;
removing said sacrifice oxide film;
and
forming a gate oxide film on said upper surface of said silicon substrate.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/875,212Filed 25 Jun 2004

Priority

JP 2003-18282226 Jun 2003

Published

US 2004/0262707 A130 Dec 2004

Granted

4 Jul 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Abstract

Facts

Application

10/875,212Filed 25 Jun 2004

Priority

JP 2003-18282226 Jun 2003

Published

US 2004/0262707 A130 Dec 2004

Granted

4 Jul 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Method of manufacturing semiconductor device

Life of this patent

Abstract

Claims10

Method of manufacturing semiconductor device

Life of this patent

Abstract

Claims10