Methods of fabricating MIM capacitors in semiconductor devices

A method of fabricating a metal-insulator-metal capacitor of a semiconductor device comprising:

• depositing a first insulating layer on a semiconductor substrate having at least one predetermined structure;
• forming a first conducting layer as a lower interconnect through the first insulating layer;
• sequentially depositing a second insulating layer, a third insulating layer, and a fourth insulating layer over the first insulating layer and the first conducting layer;
• forming a first mask pattern over the fourth insulating layer;
• forming a first dual damascene pattern by etching the fourth insulating layer using the first mask pattern as a mask;
• depositing a fifth insulating layer over the first dual damascene pattern;
• forming a second mask pattern over the fifth insulating layer;
• forming a dual damascene structure by performing an etching process using the second mask pattern and the first dual damascene pattern as a mask, respectively;
• sequentially depositing a second conducting layer and a dielectric layer along a surface of the dual damascene structure;
• selectively removing some portion of the dielectric layer so that the dielectric layer remains on an area for the capacitor;
• depositing a third conducting layer over the dielectric layer;
• and
• planarizing a top surface of the third conducting layer, the dielectric layer, and the second conducting layer by performing a chemical mechanical polish process.