US 7,071,050 B2 · Semiconductor integrated circuit device having single-element type non-volatile memory elements · patentgrep

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Abstract

A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Claims12

Dependent claims

A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a (i) first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, a control gate electrode of said first MISFET formed on said second gate insulating film, and with a (ii) third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region of a first conductivity type in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposite to said first conductivity type, in said substrate;
(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;
(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate;
and
(f) after said step (e), performing a heat treatment to form said third semiconductor region,
wherein said second semiconductor region is formed under said first semiconductor region,
wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said third semiconductor region,
wherein a junction depth of said third semiconductor region is greater than that of a junction depth of said first semiconductor region,
wherein a dose introduced in said step (e) is higher than the dose in said step (b);
(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate;
and
(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode of said second MISFET,
wherein said fourth semiconductor region serves as a drain region of said second MISFET.

12 more elements

A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode and a control gate electrode of said first MISFET formed on said second gate insulating film, and with (ii) a third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming first semiconductor regions of a first conductivity type in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of second conductivity type, opposed to said first conductivity type, in said substrate;
(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;
(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate;
and
(f) after said step (e), performing a heat treatment to form said third semiconductor region,
wherein said second semiconductor region is formed under said first semiconductor region,
wherein a channel forming region of said first MISFET is formed between said first semiconductor regions,
wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and
wherein a dose introduced in said step (e) is higher than the dose in said step (e);
(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate;
and
(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode of said second MISFET,
wherein said fourth semiconductor region serves as a drain region of said second MISFET.

12 more elements

A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region of a first conductivity type in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;
(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;
(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate;
and
(f) after said step (e), performing a heat treatment to form said third semiconductor region,
wherein said second semiconductor region is formed under said first semiconductor region,
wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said third semiconductor region;
wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and
wherein a dose introduced in said step (e) is higher than the dose in said step (b);
and
(g) after said step (f), forming side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode.

10 more elements

A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming first semiconductor regions of a first conductivity type in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;
(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;
(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate;
and
(f) after said step (e), performing a heat treatment to form said third semiconductor region,
wherein said second semiconductor region is formed under said first semiconductor region,
wherein a channel forming region of said first MISFET is formed between said first semiconductor regions,
wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and
wherein a dose introduced in said step (e) is higher than the dose in said step (b);
and
(g) after said step (f), forming side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode.

10 more elements

A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET or a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode and a control gate electrode of said first MISFET formed on said second gate insulating film, and with (ii) a third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region of a first conductivity type in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;
(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;
(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate;
(f) after said step (e), performing a heat treatment to form said third semiconductor region,
wherein said second semiconductor region is formed under said first semiconductor region,
wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said third semiconductor region,
wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said first semiconductor region, and
wherein a dose introduced in said step (e) is higher than the dose in said step (b);
(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate;
and
(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode,
wherein said fourth semiconductor region serves as a drain region of said second MISFET.

11 more elements

A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET and a second MISFET for a peripheral circuit, comprising steps of:

(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode and a control gate electrode of said first MISFET formed on said second gate insulating film, and (ii) with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming first semiconductor regions of a first conductivity type in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region of a second conductivity type, opposed to said first conductivity type, in said substrate;
(d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region;
(e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region of said first conductivity type in said substrate;
and
(f) after said step (e), performing a heat treatment to form said third semiconductor region,
wherein said second semiconductor region is formed under said first semiconductor region,
wherein a channel forming region of said first MISFET is formed between said first semiconductor regions;
wherein a junction depth of said third semiconductor region is greater than that of a junction depth of said first semiconductor region,
wherein a dose introduced in said step (e) is higher than the dose in said step (b);
(g) after said step (f), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of said first conductivity type in said substrate;
and
(h) after said steps (f) and (g), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode of said second MISFET,
wherein said fourth semiconductor region serves as a drain region of said second MISFET.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/220,723Filed 8 Sep 2005 · continuation
Priority: JP 63-2845879 Nov 1988
Published: US 2006/0014347 A119 Jan 2006
Granted: 4 Jul 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

Family

Application07/433,983Parent of this continuation · filed 9 Nov 1989
Application07/704,739Parent of this division · filed 20 May 1991
Application08/179,960Parent of this division · filed 11 Jan 1994
Application08/422,941Parent of this division · filed 17 Apr 1995
Application08/885,184Parent of this division · filed 30 Jun 1997
Application09/282,204Parent of this division · filed 31 Mar 1999
Application09/873,451Parent of this continuation · filed 5 Jun 2001
Application10/164,626Parent of this continuation · filed 10 Jun 2002
Application10/819,205Parent of this continuation · filed 7 Apr 2004
US 2006/0014347 A1Pre-grant publication · published 19 Jan 2006
US 6,960,501 B2Parent of this continuation
US 6,777,282 B2Parent of this continuation
US 6,451,643 B2Parent of this continuation
US 6,255,690 B1Parent of this division
Application09/873,451Parent of this division
US 5,904,518 AParent of this division
US 5,656,839 AParent of this division
US 5,407,853 AParent of this division
US 5,300,802 AParent of this division
Application07/704,739Parent of this continuation
US 2001/0038119 A1Published application
US 2002/0179963 A1Published application
US 2004/0191979 A1Published application
US 7,071,050 B2This patent

From the US filing history. Foreign family members aren’t listed.

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