Methods of fabricating fin field effect transistors having capping insulation layers

A method of forming a semiconductor device, the method comprising:

• selectively etching a substrate having first and second regions to form a fin active region in the first region and a planar active region in the second region;
• forming a conformal liner layer on the substrate;
• forming a insulation layer on the conformal liner layer to fill the etched region of the substrate;
• planarizing the insulation layer and conformal liner layer until top surfaces of the fin and planar active regions are exposed to form a preliminary first liner and a first device isolation layer sequentially stacked on a sidewall of the fin active region and a second liner and second device isolation layer sequentially stacked on a sidewall of the planar active region;
• forming a capping insulation layer on a top surface of the fin active region;
• selectively recessing the preliminary first liner to form a first liner on a portion of the sidewall of the fin active region for exposing a upper portion of the sidewall of the fin active region;
• forming a first gate insulation layer on at least the exposed surface of the fin active region and a second gate insulation layer on a top surface of the planar active region;
• and
• forming a first gate electrode crossing over the capping insulation layer and fin active region and a second gate electrode crossing over the planar active region,
• wherein the capping insulation layer is formed to a thickness thicker than a thickness of the first and second gate insulation layers.

A method of forming a vertical channel field effect transistor on a fin-shaped active region of a semiconductor substrate, the method comprising:

• forming an insulated gate electrode on an upper surface and opposing sidewalls of the fin-shaped active region, wherein forming the insulated gate electrode comprises forming a capping gate insulation layer on the upper surface of the fin-shaped active region to a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface when the transistor is disposed in a forward on-state mode of operation;
• and
• forming a sidewall gate insulation layer on sidewalls of the fin-shaped active region having a thickness similar to the thickness of the capping gate insulation layer,
• wherein forming the capping gate insulation layer further comprises forming the capping gate insulation layer of a material having a higher dielectric strength than the sidewall gate insulation layer.

A method of forming a vertical channel field effect transistor on a fin-shaped active region of a semiconductor substrate, the method comprising:

• forming a buffer oxide layer on the fin-shaped active region of the substrate;
• forming a liner layer on the buffer oxide layer;
• forming an insulation layer on the liner layer;
• planarizing the insulation layer, the liner layer, and the buffer oxide layer to expose an upper surface of the fin-shaped active region;
• forming a capping gate insulation layer on the upper surface of the fin-shaped active region to a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface when the transistor is disposed in a forward on-state mode of operation;
• recessing the liner layer to expose a portion the buffer oxide layer on upper sidewalls of the fin-shaped active region;
• removing the exposed portion of the buffer oxide layer to expose the upper sidewalls of the fin-shaped active region;
• forming a sidewall gate insulation layer on the exposed upper sidewalls of the fin-shaped active region;
• and
• forming a gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region,
• wherein forming the capping gate insulation layer further comprises forming the capping gate insulation layer to a thickness greater than a thickness of the sidewall gate insulation layer.

A method of forming semiconductor devices on a semiconductor substrate, comprising:

• selectively etching the substrate to form a fin-shaped active region and a planar active region;
• forming a buffer oxide layer on the fin-shaped active region and the planar active region;
• forming a liner layer on the buffer oxide layer;
• forming a insulation layer on the liner layer;
• planarizing the insulation layer, the liner layer, and the buffer oxide layer to expose upper surfaces of the fin-shaped active region and the planar active region;
• forming an oxidation barrier layer on the fin active region and the planar active region;
• patterning the oxidation barrier layer to expose the upper surface of the fin active region;
• and
• forming an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region, wherein forming the insulated gate electrode comprises:
• forming a capping gate insulation layer on the upper surface of the fin-shaped active region to a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface when the transistor is disposed in a forward on-state mode of operation;
• recessing the liner layer on the fin-shaped active region to expose a portion of the buffer oxide layer on upper sidewalls of the fin-shaped active region;
• removing the exposed portion of the buffer oxide layer to expose the upper sidewalls of the fin-shaped active region;
• forming a sidewall gate insulation layer on the exposed upper sidewalls of the fin-shaped active region;
• and
• forming a gate electrode on the upper surface and upper sidewalls of the fin-shaped active region;
• wherein a thickness of the capping gate insulation layer is greater than a thickness of the sidewall gate insulation layer.