US 7,071,040 B2Granted

Method of fabricating thin film transistor

AssigneeNEC Corporation

InventorsNaoki Matsunaga, Kenji Sera

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Abstract

A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on the substrate, and source and drain electrodes formed above source and drain regions formed in the semiconductor layer, the source and drain electrodes being composed of aluminum or aluminum alloy, the method including the steps of forming a gate electrode, implanting impurity ions into the semiconductor layer for forming the source and drain regions, forming an interlayer insulating film entirely over the substrate, forming contact holes throughout the interlayer insulating film such that the source and drain regions are exposed through the contact holes, forming an electrically conductive film composed of aluminum or aluminum alloy, in the contact holes for forming the source and drain electrodes, and thermally annealing the substrate at 275 to 350 degrees centigrade for 1.5 to 3 hours in inert atmosphere.

Claims19

Dependent claims

A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on said substrate, and source and drain electrodes formed above source and drain regions formed in said semiconductor layer, said source and drain electrodes being composed of aluminum or aluminum alloy,

said method comprising the steps of:
(a) forming a gate electrode electrically insulated from said semiconductor layer through a gate insulating film;
(b) implanting ions of impurity having a predetermined electrical conductivity, into at least a part of said semiconductor layer for forming said source and drain regions;
(c) forming an interlayer insulating film entirely over said substrate;
(d) forming contact holes throughout said interlayer insulating film such that at least a part of said source and drain regions is exposed through said contact holes;
(e) forming an electrically conductive film composed of aluminum or aluminum alloy, in said contact holes for forming said source and drain electrodes electrically connecting said source and drain regions through said contact holes;
and
(f) immediately after said step (e), thermally annealing said substrate at 275 to 350 degrees centigrade for 1.5 to 3 hours in inert atmosphere.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/639,478Filed 13 Aug 2003
Priority: JP 2002-23704815 Aug 2002
Published: US 2004/0033648 A119 Feb 2004
Granted: 4 Jul 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/0314
Characterised by the gate electrodes: of lateral top-gate TFTs comprising only a single gate
H10D 30/0316
Characterised by the gate electrodes: of lateral bottom-gate TFTs comprising only a single gate
H10D 30/0321
Of thin-film transistors [TFT]: comprising silicon, e.g. amorphous silicon or polysilicon
H10D 30/6731
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: top-gate only TFTs

Family

US 2004/0033648 A1Pre-grant publication · published 19 Feb 2004
US 7,071,040 B2This patent

From the US filing history. Foreign family members aren’t listed.

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