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US 7,067,859 B2Granted
Multi-layer staggered power bus layout design
AssigneeLSI Logic Corporation
InventorsMatthew Russell, Dushyant Narayen, Dongyi Zhou
Life of this patent
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Abstract
A bus layout design is provided which includes a first electrically conductive layer with a first bus and a second bus and a second electrically conductive layer with a first bus and a second bus. Vias are provided between the first electrically conductive layer and the second electrically conductive layer such that the first bus and the second bus of the first electrically conductive layer are electrically connected.
Claims3
A bus layout design comprising:
- a first electrically conductive layer including at least a first bus and a second bus,
- a second electrically conductive layer including at least a first bus and a second bus,
- an electrically insulating layer disposed between the first electrically conductive layer and the second electrically conductive laser,
- a plurality of vias through said electrically insulating layer conductively connecting said first electrically conductive layer and said second electrically conductive layer and arranged such that said first bus and said second bus of said first electrically conductive layer are electrically connected;
- and
- wherein said first and second electrically conductive layers and said vias are configured such that said second bus of said first electrically conductive layer is ultimately electrically connected to said first bus of said second electrically conductive layer yet said vias do not extend from said second bus of said first electrically conductive layer to said first bus of said second electrically conductive layer, wherein said plurality of vias connecting said first electrically conductive layer and said second electrically conductive layer are arranged such that said first bus and said second bus of said second electrically conductive layer are electrically connected.
3 more elements
Dependencies are inferred from the claim text.