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US 7,067,842 B1Granted
Method and apparatus for monitoring parasitic inductance
AssigneeAltera Corporation
InventorsJayakannan Jayapalan, Liping Li, Yow-Juang Liu
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AssigneeAltera Corporation
InventorsJayakannan Jayapalan, Liping Li, Yow-Juang Liu
Estimating the term…
The present invention includes a method and apparatus for measuring a parasitic inductance associated with a portion of an integrated circuit fabricated on a semiconductor substrate. A test chip for measuring the parasitic inductance is fabricated together with the integrated circuit on the semiconductor substrate. The test chip includes an LC oscillator circuit having at least one substructure that resembles the portion of the integrated circuit and at least one varactor having a capacitance adjustable by a control voltage. When the LC oscillator circuit is connected to the control voltage source and the control voltage is at a certain level, an oscillation is generated in the LC oscillator and the frequency of oscillation can be used to determine the parasitic inductance associated with the portion of the integrated circuit.
A test structure in a test area of a semiconductor substrate for measuring a parasitic inductance in an integrated circuit fabricated on the semiconductor substrate, comprising:
A method for measuring a parasitic inductance in an integrated circuit fabricated on a semiconductor substrate, comprising:
A test structure in a test area adjacent at least one integrated circuit on a semiconductor wafer, the test structure comprising an LC oscillator circuit having an oscillation frequency related to a parasitic inductance associated with a subcircuit in the at least one integrated circuit.
A test structure in a test area of a semiconductor substrate for measuring a parasitic inductance in an integrated circuit fabricated on the semiconductor substrate, comprising:
Dependencies are inferred from the claim text.