US 7,067,390 B2 · Method for forming isolation layer of semiconductor device

Abstract

Disclosed is a method for forming an isolation layer of a semiconductor device. The method includes the steps of providing a semiconductor substrate having a predetermined isolation region, sequentially forming a pad oxide layer and a pad nitride layer exposing the predetermined isolation region on the semiconductor substrate, forming a trench through etching the semiconductor substrate by a predetermined thickness using the pad nitride layer as a mask, forming a wall oxide layer at a side wall of the trench, sequentially forming a nitride layer and an oxide layer on a trench structure including the wall oxide layer, forming an Al2O3 layer on an entire surface of a resultant structure, planarizing the Al2O3 layer through polishing the Al2O3 layer, and forming the isolation layer by removing the pad nitride layer.

Drawings

Drawings are temporarily unavailable. Open the PDF at USPTO

Drawings

Claims10

Dependent claims

A method for forming an isolation layer of a semiconductor device, the method comprising the steps of:

i) providing a semiconductor substrate having a predetermined isolation region;
ii) sequentially forming a pad oxide layer and a pad nitride layer exposing the predetermined isolatIon region on the semiconductor substrate;
iii) forming a trench through etching the semiconductor substrate by a predetermined thickness using the pad nitride layer as a mask;
iv) forming a wall oxide layer at a side wall of the trench;
v) sequentially forming a nitride layer and an oxide layer on a trench structure including the wall oxide layer;
vi) forming an Al2O3 layer on an entire surface of a resultant structure, wherein the Al2O3 layer has a wet etch rate less than 0.5 Å /sec in HF solution having a ratio of 50:1 to prevent damage to the Al2O3 layer during a subsequent wet etching step;
vii) planarizing the Al2O3 layer through polishing the Al3O3 layer, and
viii) removing the pad nitride layer and the pad oxide layer by one or more wet etching processes without damaging the Al2O3 layer.

5 more elements

Dependencies are inferred from the claim text.

Description1,968 words

Summary1,044 words

#1. Field of the Invention

#The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming an insulation layer of a semiconductor device capable of preventing an oxide layer from being damaged in a following wet-etch process by using an Al2O3 layer as the oxide layer filling a trench in an STI (shallow trench isolation) process of a DRAM device.

#2. Description of the Prior Art

Brief description of the drawings2 figures

#The above object, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

#FIGS. 1a to 1d are sectional views showing a conventional method for forming an isolation layer of a semiconductor device by using an STI process; and

#FIGS. 2a to 2d are sectional views showing a method for forming an isolation layer of a semiconductor device according to one embodiment of the present invention.

Detailed description843 words

#Hereinafter, a method for forming an isolation layer of a semiconductor device according to one embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description on the same or similar components will be omitted.

#FIGS. 2a to 2d are sectional views showing a method for forming an isolation layer of a semiconductor device according to one embodiment of the present invention.

#As shown in FIG. 2a, according to the method for forming the isolation layer of the semiconductor device of the present invention, a silicon substrate 20 having a predetermined isolation region is provided. Then, after a pad oxide layer 21 having a thickness of about 100Å and a pad nitride layer 22 having a thickness of about 1,400Å are sequentially formed on the silicon substrate 20, a photoresist film is coated on the pad nitride layer 22. Thereafter, an exposure and development process is carried out with respect to the photoresist film, thereby forming a photoresist film pattern 30 exposing the predetermined isolation region.

Facts

Application

10/889,480Filed 12 Jul 2004

Priority

KR 10-2003-008492027 Nov 2003

Published

US 2005/0118786 A12 Jun 2005

Granted

27 Jun 2006

Term ended

9 Nov 2024

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 120 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification3 codes

H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/0145
Using trench refilling with dielectric materials, e.g. shallow trench isolations: of trenches having shapes other than rectangular or V-shape
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Timeline

27 Nov 2003Priority claimedKR 10-2003-0084920
12 Jul 2004Application filedUS 10/889,480
12 Jul 2004Assigned to Hynix Semiconductor Inc.assignment of assignor's interest
2 Jun 2005PublishedUS 2005/0118786 A1
27 Jun 2006GrantedUS 7,067,390 B2
9 Mar 2014Assigned to SK Hynix Incchange of name
9 Mar 2014Assigned to Intellectual Discovery Co., Ltd.assignment of assignor's interest
9 Nov 2024Term endedEstimated, includes 120 days of adjustment

Method for forming isolation layer of semiconductor device

Life of this patent

Method for forming isolation layer of semiconductor device

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims10

Description1,968 words

Drawings

Classification3 codes

Life of this patent

Description1,968 words