Semiconductor device and method for fabricating the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsHiroaki Nakaoka, Kentaro Nakanishi, Hiroyuki Umimoto, Atsuhiro Kajiya
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Abstract
As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.
Claims11
A method for fabricating a semiconductor device, comprising the steps of:
- a) forming a gate insulating film over an active region of a substrate;
- b) forming a silicon film over the gate insulating film;
- c) patterning the silicon film, thereby forming a gate electrode;
- d) performing ion implantation of an impurity using at least the gate electrode as a mask, thereby forming a source/drain region including a heavily doped impurity region;
- e) performing first thermal treatment for activating the impurity introduced into the gate electrode;
- and
- f) performing second thermal treatment for activating the impurity introduced into the gate electrode and the source/drain region at a higher temperature for a shorter time than the first thermal treatment is performed,
- wherein the active region includes an NMISFET formation region and a PMISFET formation region,
- wherein in the step c), a gate electrode of the NMISFET and a gate electrode of the PMISFET are formed,
- wherein in the step d), an n-type impurity and a p-type impurity are separately ion-implanted into the NMISFET formation region and the PMISFET formation region, respectively,
- wherein after the step b) and before the step c), an n-type impurity is ion-implanted into part of the silicon film located in the NMISFET formation region while introduction of an impurity is not performed to part of the silicon film located in the PMISFET formation region, and a p-type impurity is introduced into the gate electrode of the PMISFET.
A semiconductor device comprising:
- a substrate;
- a gate insulating film formed over an active region of the substrate:
- a gate electrode formed over the gate insulating film and including a lower gate electrode made of polysilicon having a large gain size and an upper gate electrode having a smaller grain size than that of the lower electrode and including at least a single polysilicon layer;
- and
- a source/drain region formed in each of respective regions of the active region located on both sides of the gate electrode and including a heavily doped impurity region,
- wherein the thickness of the lower gate electrode is larger than a dimension by which the heavily doped impurity region of the source/drain region is magnified when thermal treatment for activating the impurity in the gate electrode is performed and smaller than the thickness of the upper gate electrode.
Dependencies are inferred from the claim text.