Silicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness
AssigneeInternational Business Machines Corporation
InventorsTak H. Ning, Devendra K. Sadana
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Abstract
The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.
Claims8
A method of forming a semiconductor structure comprising:
- providing a starting SOI wafer which comprises a buried insulating region sandwiched between a bottom Si-containing layer and a top Si-containing layer, said top Si-containing layer having a substantially uniform thickness;
- thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon to provide at least a first region within said top Si-containing layer having a first thickness and at least a second region having a second thickness, where said first thickness is different from said second thickness;
- forming a fully depleted CMOS device in said first region having source and drain regions in contact with the underlying buried insulating region;
- and
- forming a partially depleted CMOS device in said second region having a quasi-neutral device substrate region.
A method of forming a semiconductor structure comprising:
- providing a starting SOI wafer which comprises a buried insulating region sandwiched between a bottom Si-containing layer and a top Si-containing layer, said top Si-containing layer having a substantially uniform thickness;
- thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon to provide at least a first region within said top Si-containing layer having a first thickness and at least a second region having a second thickness, where said first thickness is different from said second thickness;
- forming a fully depleted CMOS device in said first region of the top Si-containing layer having source and drain regions in contact with the underlying buried insulating region and no quasi-neutral device substrate region;
- forming a first partially depleted CMOS device in said second region of the top Si-containing layer having source and drain regions in contact with the underlying buried insulating region and having a quasi-neutral device substrate region;
- and
- forming a second partially depleted CMOS device located in a relatively thicker silicon region of the top Si-containing layer having source and drain regions not in contact with the underlying buried insulating region and having a quasi-neutral device substrate region.
A method of forming a semiconductor structure comprising:
- providing a starting SOI wafer which comprises a buried insulating region sandwiched between a bottom Si-containing layer and a top Si-containing layer, said top Si-containing layer having a substantially uniform thickness;
- thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon to provide at least a first region within said top Si-containing layer having a first thickness and at least a second region having a second thickness, where said first thickness is different from said second thickness;
- forming a CMOS device in said first region;
- and
- forming a bipolar device in said second region, said bipolar device is a vertical transistor including a collector, a base and an emitter.
Dependencies are inferred from the claim text.