US 7,067,354 B2 · Electrical die contact structure and fabrication method

Abstract

A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The surface portion of the top protective layer includes electrical contact pads that are electrically connected with electrical contact pad extensions and with the integrated circuit. The second surface of the semiconductor substrate includes a multiplicity of backside electrical connectors that are in overlapping electrical contact with corresponding electrical contact pad extensions forming lap joint electrical connections between the backside electrical connectors and the corresponding electrical contact pad extensions. Methods for constructing such devices and connections are also disclosed.

Claims11

Dependent claims

A method of forming an edge mounted electrical connection to a semiconductor die comprising:

providing a substrate having a plurality of semiconductor dies and associated electrical contact pads formed thereon;
forming lap joint electrical connection with the associated electrical contact pads;
forming solder connections to the lap joint electrical connections;
and
singulating the substrate into a plurality of individual dies.

2 more elements

A method for producing electrical die contact structures for integrated circuit devices, the method including the steps of:

providing a plurality of integrated circuits on a semiconductor wafer having a front side and a backside, each of the integrated circuits being delineated from other integrated circuits on the wafer by a plurality of saw streets and each integrated circuit including a multiplicity of electrical contact pads with contact pad extensions that extend into the saw streets;
attaching a front side protective layer to a front side surface of the wafer;
removing material from the backside of the wafer in the saw streets until a bottom surface of the contact pad extensions is exposed, thereby defining notches along edges of the integrated circuit devices;
forming lap joint electrical connections to the contact pad extensions;
forming on the backside of the wafer solderable electrical contacts that are electrically interconnected with the lap joint electrical connections;
and
separating the plurality of integrated circuit devices into individual devices.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/871,337Filed 18 Jun 2004 · continuation in part

Priority

13 May 2002

Published

US 2004/0229405 A118 Nov 2004

Granted

27 Jun 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10F 39/804
Constructional details of image sensors: containers or encapsulations
H10W 20/40
Interconnections in chips, wafers or substrates: interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or…
H10F
Solar cells and light sensors
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Family

Application10/145,295Parent of this continuation-in-part · filed 13 May 2002

Application10/310,724Parent of this division · filed 4 Dec 2002

US 2004/0229405 A1Pre-grant publication · published 18 Nov 2004

US 6,781,244 B2Parent of this division

Application10/145,295Parent of this division

US 2003/0209772 A1Published application

US 7,340,181 B1Related patent

US 7,067,354 B2This patent

From the US filing history. Foreign family members aren’t listed.

Electrical die contact structure and fabrication method

Life of this patent

Electrical die contact structure and fabrication method

Life of this patent

Abstract

Claims11