Semiconductor memory device and portable electronic apparatus

A semiconductor memory device, comprising:

• a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode, each memory function unit having a retaining region for retaining charges, at least a part of the retaining region existing over one of the diffusion regions;
• a word line connected to the gate electrode of the memory cell;
• and
• a negative voltage switching circuit, connected to the word line, for connecting a first voltage having a voltage level lower than zero volt to the gate electrode of the memory cell during an erasing period of the memory cell, wherein
• the negative voltage switching circuit includes:
• a switching transistor connected to the word line and a first voltage source;
• a pull-up circuit, connected to a control terminal of the switching transistor and selectively connected to a second voltage source having a voltage level higher than zero volt, for connecting the second voltage source to a control terminal of the switching transistor when the pull-up circuit is connected to the second voltage source such that the switching transistor does not connect the first voltage source to the gate electrode of the memory cell via the word line;
• and
• a pull-down circuit, connected to the first voltage source and the control terminal of the switching transistor, for connecting the first voltage source to the control terminal of the switching transistor when the pull-up circuit is not connected to the second voltage source such that the switching transistor connects the first voltage source to the memory cell via the word line.

A semiconductor memory device, comprising:

• a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode, each memory function unit having a retaining region for retaining charges, at least a part of the retaining region existing over one of the diffusion regions;
• a voltage switching circuit for applying a voltage to the gate electrode of the memory cell;
• a switching transistor connected to an output of the voltage switching circuit and a first voltage source having a voltage level lower than zero volt;
• a first transistor, connected to a control terminal of the switching transistor and selectively connected to a second voltage source having a voltage level higher than zero volt, for connecting the second voltage source to the control terminal of the switching transistor when the switching transistor is connected to the second voltage source such that the switching transistor does not connect the first voltage source to the output;
• and
• a first resistor, connected to the first voltage source and the control terminal of the switching transistor, for connecting the first voltage source to the control terminal of the switching transistor when the switching transistor is not connected to the second voltage source such that the switching transistor connects the first voltage source to the output.