ESD protection circuit with tunable gate-bias
AssigneeSilicon Integrated Systems Corp.
InventorsMing-Dou Ker, Wen-Yu Lo
Life of this patent
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AssigneeSilicon Integrated Systems Corp.
InventorsMing-Dou Ker, Wen-Yu Lo
Estimating the term…
An ESD protection circuit with tunable gate-bias coupled between a first and second pads for receiving power supply voltages. The ESD protection circuit includes a diode, a resistor coupled between the cathode of the diode and the first pad, a capacitor coupled between the cathode of the diode and the second pad, a first transistor of a first conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the second pad, a second transistor of a second conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the first pad, and a third transistor of the first conductivity type having a gate coupled to the anode of the diode, a drain coupled to the first pad and a source coupled to the second pad.
An ESD protection circuit with tunable gate-bias coupled between a first and second pad respectively for receiving a first and second power supply voltage, the ESD protection circuit comprising:
An ESD protection circuit with tunable gate-bias coupled between a first and second pad respectively for receiving a first and second power supply voltage, the ESD protection circuit comprising:
An ESD protection circuit with tunable gate-bias coupled between a first and second pad respectively far receiving a first and second power supply voltage, the ESD protection circuit comprising:
An ESD protection circuit with tunable gate-bias coupled between a first and second pad respectively for receiving a first and second power supply voltage, the ESD protection circuit comprising:
An ESD protection circuit with tunable gate-bias coupled between a first and second pad respectively for receiving a first and second power supply voltage, die ESD protection circuit comprising:
An ESD protection circuit with tunable gate-bias coupled between a first and second pad respectively for receiving a first and second power supply voltage, the ESD protection circuit comprising:
Dependencies are inferred from the claim text.