US 7,064,373 B2 · Architecture and fabrication method of a vertical memory cell

Abstract

A vertical memory cell comprises a storage capacitor, the inner electrode of which is formed in a deep trench, and a vertical selector transistor. The selection transistor has an upper source/drain region and a lower source/drain region, which has emerged by outdiffusion of a dopant from the inner electrode. A gate electrode, which in each case controls a current flow between two assigned source/drain regions, is formed, in segments, as a segment of an addressing line arranged row-wise in active trenches. The provision of an auxiliary structure in the active trenches enables the addressing lines to be vertically positioned in the active trenches independently of a depth of the active trenches. Leakage currents which occur in overlap regions of the addressing lines with the inner electrode or the lower source/drain region are reduced.

Claims19

Dependent claims

A vertical memory cell array containing at least one vertical memory cell, the memory cell comprising:

a storage capacitor formed in a deep trench in a semiconductor substrate and containing an inner electrode arranged in the deep trench;
a selection transistor formed essentially between the substrate surface of the semiconductor substrate and an upper edge of the inner electrode;
a lower source/drain region in the selection transistor connected to the inner electrode and an upper source/drain region;
a selection transistor gate electrode formed, at least in segments, as segments of an addressing line arranged in active trenches that extend from the substrate surface to below the upper edge of the inner electrode and insulate adjacent memory cells from one another;
and
an auxiliary structure extending essentially from a bottom of an active trench as far as the upper edge of the inner electrode, wherein the addressing line is formed in the region between the substrate surface and the upper edge of the auxiliary structure.

3 more elements

Dependencies are inferred from the claim text.

Architecture and fabrication method of a vertical memory cell

Life of this patent

Architecture and fabrication method of a vertical memory cell

Life of this patent

Abstract

Claims19