Low leakage one transistor static random access memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPin-Shyne Chin, Wen-Jye Yue, Hsien-Chin Peng
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Abstract
The invention forms a 1T Static Random Access Memory (SRAM) with a low concentration cell node region and a higher concentration bit line region (e.g., second bit line region). The method of the invention forms a 1T Static Random Access Memory (SRAM) that uses a resist mask to block a high concentration implant into the cell node region, but allows the high concentration implant into the bit line region to form a second (high concentration) bit line. The invention's 1T SRAM, with the low concentration cell node, has reduced p-n junction leakage at the cell node and increase date retention time.
Claims9
A 1T SRAM comprising:
- a word line structure on a substrate;
- a capacitor plate structure on said substrate;
- a cell node region in said substrate between said word line structure and said capacitor plate structure, said cell node region having an impurity concentration;
- and
- a bit line region in said substrate adjacent to said word line structure;
- wherein said bit line region includes a first region having an impurity concentration greater than the impurity concentration of said cell node region.
Dependencies are inferred from the claim text.