Triggered back-to-back diodes for ESD protection in triple-well CMOS process

A method of forming an ESD protection device comprising:

• a) forming a n-doped region and a p-doped region in a p-well in a semiconductor structure;
• said n-doped region and said p-doped region are spaced;
• b) forming a n-well and a deep n-well that surround said p-well on the sides and bottom;
• c) connecting electrically a first I/O pad to said n-doped region;
• d) connecting electrically a trigger circuit to said first I/O and said p-doped region;
• e) connecting electrically a second I/O pad to said n-well;
• whereby a parasitic bipolar transistor is comprised of the n-doped region functioning as a collector terminal, the P− well functioning as a base terminal, and the deep p-well functioning as the emitter terminal;
• whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.

A method for using an ESD protection device comprising the steps of:

• (1) providing:
• a) a n-doped region and a p-doped region in a p-well in a semiconductor structure;
• said n− doped region and said p-doped region are spaced;
• b) a n-well and a deep n-well surrounding said p-well on the sides and bottom;
• c) a first I/O pad connected to said n-doped region;
• d) a trigger circuit connected to said first I/O pad and said p-doped region;
• e) a second I/O pad connected to said n-well;
• f) a parasitic bipolar transistor is comprised of the n-doped region functioning as a collector terminal, the P− well functioning as a base terminal, and the deep p-well functioning as the emitter terminal;
• (2) charging said p-well using the trigger circuit under an ESD condition and turning on said parasitic bipolar transistor.

A method of using a ESD protection device comprising the steps of:

• (1) providing:
• a) a n-doped region and a p-doped region in a p-well in a semiconductor structure;
• said n− doped region and said p-doped region are spaced;
• b) a n-well and a deep n-well surrounding said p-well on the sides and bottom;
• c) a first I/O pad connected to said n-doped region;
• d) a trigger circuit connected to said first I/O pad and said p-doped region;
• e) a second I/O pad connected to said n-well;
• f) a parasitic bipolar transistor is comprised of the n-doped region functioning as a collector terminal, the P− well functioning as a base terminal, and the deep p-well functioning as the emitter terminal;
• whereby under an ESD condition, the p-well is charged positive using the trigger circuit and said parasitic bipolar transistor can be turned on;
• g) a N-doped ring region laterally surrounding said p-doped region whereby said N-doped ring region and said deep n-well increase the resistance of the parasitic bipolar transistor thereby increasing the pinch off during an ESD event
• (2) reverse-biasing said N-doped ring region during an ESD event to increase the effective resistance seen by the injected current in the P-doped region by said trigger circuit into p-well.