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US 7,064,061 B2Granted
Process for fabricating interconnect networks
AssigneesSTMicroelectronics S.r.l., Commissariat a l'Energie Atomique
InventorsGérard Passemard, Emmanuel Sicurani, Charles Lecornec
Life of this patent
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Abstract
The process includes depositing a filling material in trenches formed in at least one layer of dielectric so as to fill open pores in the dielectric. The filling material is intended to prevent the subsequent diffusion of the interconnect metal and/or of a metal of a diffusion barrier, and may be non-porous. The filling material preferably has a low dielectric constant.
Claims16
A semiconductor device comprising:
- an interconnect network comprising at least one dielectric layer having a trench, and at least one interconnect formed in the trench, the dielectric layer having pores;
- a filling material filling only in the pores between the dielectric layer and the interconnect;
- and
- a diffusion barrier layer between the interconnect and the dielectric layer, and in contact with the dielectric layer and the filling material.
1 more element
A semiconductor device comprising:
- an interconnect network comprising a dielectric layer having a trench, and an interconnect formed in the trench, the dielectric layer having pores;
- a filling material only in the pores;
- and
- a diffusion barrier layer covering and in contact with the filled pores and the dielectric layer.
1 more element
Dependencies are inferred from the claim text.