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US 7,064,042 B1Granted
Self aligned compact bipolar junction transistor layout, and method of making same
AssigneeIntel Corporation
InventorsShahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green, Anand Murthy
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Abstract
The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.
Claims5
A process for manufacturing a device on a substrate comprising:
- forming in the substrate, deep and shallow trench isolations, buried layers and collector wells for the device;
- forming a layer of etch resistant material over the substrate;
- defining an active base region of the device by removal of the layer of etch resistant material over a portion of the surface of the substrate to expose an active base region;
- forming a boron doped oxide film over the base region and the layer of etch resistant material;
- anisotropically removing the boron doped oxide film from the active base region and the layer of etch resistant material leaving doped spacers of boron dope oxide film adjacent the active base region at a perimeter of the active base region;
- depositing an epitaxial polycrystalline film over the layer of etch resistant material and an epitaxial crystalline film over the active base region, wherein the epitaxial polycrystalline film and the epitaxial crystalline film form a crystalline/polycrystalline boundary.
3 more elements
Dependencies are inferred from the claim text.