US 7,064,032 B2 · Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells

Abstract

A method for forming a non-volatile memory cell includes depositing an oxide layer over a component stack including a dielectric layer over a first conductive layer. A portion of an upper section of the oxide layer is removed such that the dielectric layer is exposed. The dielectric layer and a remainder of the oxide layer upper section are removed such that upper surfaces of the oxide layer and the first conductive layer are substantially planar. A second conductive layer is formed over the upper surfaces of the first conductive layer and the oxide layer. A non-volatile memory array is formed including multiple spaced and parallel bit lines in a substrate surface. Multiple stacked layers, including an electron trapping layer, are on the substrate surface over the bit lines. Multiple spaced word lines are over the stacked layers. The word lines are parallel to one another and perpendicular to the bit lines.

Claims13

Dependent claims

A method for fanning at least one non-volatile memory cell, comprising:

(a) forming a first oxide layer, an electron trapping layer, a second oxide layer, a first electrically conductive layer, and a dielectric layer on a surface of a substrate in that order;
(b) patterning the dielectric layer and the first electrically conductive layer, thereby forming at least one component stack;
(c) depositing a third oxide layer over and beside the at least one component stack;
(d) removing a portion of an upper section of the third oxide layer opposite the second oxide layer such that an upper portion of the dielectric layer is exposed through the third oxide layer;
(e) removing the dielectric layer and a remaining portion of the upper section of the third oxide layer such that an elevation of an upper surface of the third oxide layer above the surface of the substrate is substantially equal to an elevation of an upper surface of the patterned first electrically conductive layer;
and
(f) forming a second electrically conductive layer over upper surfaces of the patterned first electrically conductive layer and the third oxide layer.

4 more elements

Dependencies are inferred from the claim text.

Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells

Life of this patent

Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells

Life of this patent

Abstract

Claims13