Distributed delay-locked-based clock and data recovery systems
AssigneeThe Regents of the University of California
InventorsRavindran Mahanavelu, Payam Heydari
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Abstract
A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.
Claims18
A clock and data recovery system for aligning a local clock with a data stream, comprising:
- a first section configured to compare the phase of a data stream with the phase of a local clock and output a control voltage corresponding to the difference in phase between the data stream and clock, wherein the first section comprises a half-rate phase detector configured to compare the phase of the incoming data stream with a first and a second clock signal, the second clock signal being out of phase with the first clock signal, and a charge pump coupled with a the phase detector;
- and
- a variable delay line comprising a plurality of variable impedance LC subcircuits responsive to the control voltage, the variable delay line configured to delay the local clock by an amount corresponding to the control voltage, wherein the delayed local clock is fed back to the first section.
Dependencies are inferred from the claim text.