Method to shrink cell size in a split gate flash

A method to form split gate flash devices in an integrated circuit device comprising:

• forming a dielectric layer overlying a substrate;
• forming a polysilicon layer overlying said dielectric layer;
• forming a silicon oxide layer overlying said polysilicon layer;
• forming a patterned masking layer overlying and selectively exposing said silicon oxide layer;
• thereafter oxidizing said polysilicon layer to increase thickness of said exposed silicon oxide layer wherein said thickened silicon oxide layer encroaches under the edges of said masking layer and wherein said silicon oxide layer does not thicken under other interior areas of said masking layer;
• thereafter removing said masking layer;
• thereafter etching said silicon oxide layer to selectively expose said polysilicon layer where said silicon oxide layer did not thicken;
• etching through said exposed polysilicon layer to thereby form floating gates;
• thereafter removing said silicon oxide layer;
• thereafter etching said floating gates to selectively expose said substrate;
• thereafter forming a second dielectric layer overlying said floating gates and said exposed substrate;
• depositing a conductor layer overlying said second dielectric layer;
• and
• etching back said conductor layer to form control gates on sidewalls of said floating gates in the formation of said split gate flash devices in the manufacture of said integrated circuit device.

A method to form MOS gates in an integrated circuit device comprising:

• forming a dielectric layer overlying a substrate;
• forming a polysilicon layer overlying said dielectric layer;
• forming a patterned masking layer overlying said polysilicon layer, said patterned masking layer having an opening;
• oxidizing through said opening said polysilicon layer to form a first silicon oxide layer at the bottom of said opening, wherein said first silicon oxide layer encroaches under the edges of said masking layer;
• removing said masking layer after formation of said first silicon oxide layer and exposing said polysilicon layer;
• etching through said exposed polysilicon layer and using said first silicon oxide layer as a mask to thereby form MOS floating gates in the manufacture of said integrated circuit device;
• and
• removing said first silicon oxide layer after said step of etching through said exposed polysilicon layer.