Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM

A method of forming an integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region including the steps as follows:

• forming a sacrificial polysilicon layer over said array region followed by formation of a gate oxide layer over said device;
• forming a thick polysilicon layer in both said array region where word lines are located and said support region where the logic circuits are located;
• removing said thick polysilicon layer only over the array region and removing the sacrificial polysilicon layer;
• then precleaning the device;
• then depositing a thin polysilicon layer in both said array region and said support region,
• then depositing a metallic conductor coating including at least an elemental metal layer portion over said thin polysilicon layer;
• and
• then forming word lines and gate electrodes in said array region and in said support region respectively.

A method of forming an integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region including the steps as follows:

• forming a thick polysilicon layer having a first thickness of greater than or equal to 500Å over both said array region where word lines are located and over said support region where said logic circuits are located;
• then removing said thick polysilicon layer only from said array region;
• then depositing a thin polysilicon layer over both said array region and over said support region, said thin polysilicon layer having a second thickness of less than or equal to 300Å;
• then depositing a metallic conductor coating including at least an elemental metal layer portion over said thin polysilicon layer;
• and
• then forming word lines in said array region from said thin polysilicon layer and forming gate electrodes in said support region from said thick polysilicon layer and said thin polysilicon layer thereabove.