Method of manufacturing semiconductor device having shallow trench isolation (STI)
AssigneeSamsung Electronics Co., Ltd.
InventorSung-Hoan Kim
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device having a shallow trench isolation includes steps of forming a mask layer on a semiconductor substrate, forming a shallow trench in a semiconductor substrate using the mask layer, forming at least one step in the semiconductor substrate at the top of the shallow trench, and then forming a liner layer over the entire surface of the semiconductor substrate so as to line the shallow trench and thereby offer protection during subsequent oxidation. When the mask layer is subsequently removed, the at least one step in the semiconductor substrate allows portions of the liner layer extending outside the shallow trench to be removed without creating problematic dents in the structure.
Claims37
A method of manufacturing a semiconductor device having a shallow trench isolation (STI) structure, comprising:
- a) providing a semiconductor substrate having a field region and an active region;
- b) forming a first insulating layer and mask layer in that sequence on the semiconductor substrate;
- c) patterning the first insulating layer and mask layer, and forming a shallow trench in the semiconductor substrate;
- d) forming at least one step in the semiconductor substrate at the top of the shallow trench;
- e) forming a second insulating layer that covers an inner surface of the semiconductor substrate defining the shallow trench;
- f) subsequently forming a liner layer over the entire surface of the semiconductor substrate;
- g) subsequently forming a third insulating layer over the entire surface of the semiconductor substrate to such a thickness that the third insulating layer fills the shallow trench;
- h) polishing the third insulating layer, the liner layer and the mask layer to planarize the same, until a portion of the mask layer is exposed;
- and
- i) subsequently performing an etching process to remove the first insulating layer.
A method of manufacturing a semiconductor device having a shallow trench isolation (STI) structure, comprising:
- a) providing a semiconductor substrate having a field region and an active region;
- b) forming a first insulating layer and a mask layer in that sequence on the semiconductor substrate, and patterning the first insulating layer and the mask layer to expose the field region of the semiconductor substrate;
- c) forming at least one step in the semiconductor substrate in the exposed field region at a location adjacent edges of the active region of the semiconductor substrate;
- d) subsequently forming a shallow trench in the field region of the semiconductor substrate while maintaining the at least one step at the top of the shallow trench;
- e) forming a second insulating layer that covers an inner surface of the semiconductor substrate defining the shallow trench;
- f) subsequently forming a liner layer over the entire surface of the semiconductor substrate;
- g) subsequently forming a third insulating layer over the entire surface of the semiconductor substrate to such a thickness that the third insulating layer fills the shallow trench;
- h) polishing the third insulating layer, the liner layer and the mask layer to planarize the same, until a portion of the mask layer is exposed;
- and
- i) subsequently performing an etching process to remove the first insulating layer.
A method of manufacturing a semiconductor device having a shallow trench isolation (STI) structure, comprising:
- a) providing a semiconductor substrate having a field region and an active region located on both sides of the field region;
- b) forming a first insulating layer and mask layer in that sequence on the semiconductor substrate;
- c) forming a shallow trench in the field region semiconductor substrate using the mask layer as a mask;
- d) forming at least one step at the top of the semiconductor substrate in the field region thereof adjacent the active region;
- e) forming a second insulating layer that covers an inner surface of the semiconductor substrate that defines the shallow trench;
- f) subsequently forming a liner layer over the entire surface of the semiconductor substrate so that the liner layer forms a liner over the shallow trench, the at least one step and the mask layer;
- g) subsequently forming a third insulating layer over the entire surface of the semiconductor substrate to such a thickness that the third insulating layer fills the shallow trench;
- h) polishing the third insulating layer, the liner layer and the mask layer to planarize the same, until a portion of the mask layer is exposed;
- and
- i) subsequently performing an etching process to remove the first insulating layer.
Dependencies are inferred from the claim text.