Stacked columnar 1T-nMTJ structure and its method of formation and operation
AssigneeMicron Technology, Inc.
InventorsHasan Nejad, Mirmajid Seyyedy
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Abstract
This invention relates to an array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of cells each column being provided in a respective stacked memory layer.
Claims8
A method of reading a resistive memory device comprising a plurality of stacked layers of resistive memory cells, each layer comprising an array of memory cells arranged in rows and columns in an X-Y plane, said plurality of stacked layers forming a plurality of slices of resistive memory cells, each slice arranged in rows and columns in Y-Z planes and having an associated access transistor, said method comprising:
- applying a voltage to a read/write line associated with a selected memory cell from one of said plurality of slices of resistive memory cells;
- activating an access transistor associated with said selected memory cell;
- coupling selected memory cell through said selected memory cell to a sense amplifier;
- and
- sensing a logic state of said selected memory cell.
A method of reading a resistive memory device comprising a plurality of stacked layers of resistive memory cells, each layer comprising an array of memory cells arranged in rows and columns in an X-Y plane, said plurality of stacked layers forming a plurality of slices of resistive memory cells, each slice arranged in rows and columns in Y-Z planes and having an associated access transistor, said method comprising:
- decoding an address associated with a selected memory cell in said memory device;
- applying a voltage to a read/write line associated said address;
- activating an access transistor associated with said address;
- and
- sensing a logic state of said selected memory cell at said address.
Dependencies are inferred from the claim text.