US 7,023,053 B2Granted

Differential transistor pair

AssigneeInfineon Technologies AG

InventorsJohan Sjöström, Torkel Arnborg

Life of this patent

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Abstract

A differential transistor pair comprises a plurality of transistor cells in a substrate. Each cell comprises first drain regions at the respective edge of the cell, and a second drain region in between. Source regions are located between the respective first drain region and the second drain region. First gate regions are located between the respective first drain region and the source regions, and second gate regions are located between the source regions and the second drain region. The first drain regions of all cells are interconnected to a common first drain terminal, and the second drain region of all cells are interconnected to a common second drain terminal. The first gate regions of all cells are interconnected to a common first gate terminal, and the second gate regions of all cells are interconnected to a common second gate terminal.

Claims5

Dependent claims

A differential transistor pair comprising a first and second transistor, said first and second transistors comprising at least one transistor cell provided in a substrate, the at least one cell comprising:

a first and a second drain/collector region belonging to the first transistor of said differential transistor pair and arranged separated from each other,
a third drain/collector region belonging to the second transistor of said differential transistor pair, and arranged between said first and second drain/collector regions,
a first source/emitter region arranged between said first drain/collector region and said third drain/collector region, and a second source/emitter region arranged between said second drain/collector region and said third drain/collector region, said source/emitter regions being common to both transistors of the differential transistor pair,
a first and a second gate/base region belonging to the first transistor of said differential transistor pair, said first gate/base region being arranged between said first drain collector region and the first source/emitter region, and said second gate/base region being arranged between said second drain/collector region and the second source/emitter region, and
a third and a fourth gate/base region belonging to the second transistor of said differential transistor pair, said third gate/base region being arranged between said third drain/collector region and the first course/emitter region, and said fourth gate/base region being arranged between said third drain/collector region and the second source/emitter region.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/848,811Filed 19 May 2004 · continuation
Priority: SE 01041166 Dec 2001
Published: US 2004/0212020 A128 Oct 2004
Granted: 4 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
H10D 84/83125
Of only insulated-gate FETs [IGFET]: the IGFETs characterised by having shared source or drain regions
H10D
Inorganic electric semiconductor devices