Layout of a flash memory having symmetric select transistors
AssigneeMacronix International Co., Ltd.
InventorsJen-Ren Huang, Ming-Hung Chou
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Abstract
A layout of flash memory having symmetric select transistors includes a memory cell array and a polysilicon gate. The polysilicon gate forms a plurality of select transistors in coordination with a plurality of pairs of sources/drains, so as to connect to the memory cell array. The polysilicon is perpendicularly extended toward a direction of the memory cell array, thereby overcoming a drawback as select transistors being unsymmetrical in a prior flash memory structure.
Claims4
A layout of a flash memory having a plurality of symmetric select transistors, comprising:
- a memory cell array;
- polysilicon gates of the plurality of symmetric select transistors extending in a direction perpendicular to a side of the memory cell array and cooperating with a plurality of pairs of sources/drains for forming the plurality of symmetric select transistors;
- and
- wires connecting the plurality of symmetric select transistors and the memory cell array.
A layout of a flash memory having a plurality of symmetric select transistors, comprising:
- a memory cell array;
- and
- polysilicon gates corresponding to the plurality of symmetric select transistors extending in a direction perpendicular to a side of the memory cell array;
- wherein the plurality of symmetric select transistors are arranged substantially symmetric with respect to the side of the memory cell array.
Dependencies are inferred from the claim text.