Field-effect transistor with horizontal self-aligned gates and the production method therefor
AssigneeCommissariat a l'Energie Atomique
InventorSimon Deleonibus
Life of this patent
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Abstract
A field-effect transistor including: a support substrate, an active area forming a channel; a first active gate which is associated with a first face of the active area; source and drain areas which are formed in the active area and which are self-aligned on the first gate; a second insulated gate which is associated with a second face of the active region opposite the first face of the active region. According to the invention, the second gate is self-aligned on the first gate and, together with the first gate, forms a mesa structure on a support substrate.
Claims21
A field-effect transistor comprising:
- a support substrate,
- an active region comprising a channel,
- a first insulated gate associated with a first face of the active region,
- source and drain regions formed in the active region and self-aligned on the first insulated gate,
- a second insulated gate associated with a second face of the active region, opposite the first face of the active region, wherein
- the second insulated gate, which is the closest to the support substrate, is self-aligned on the first insulated gate and the first and second insulated gates form a mesa structure on the support substrate, and wherein
- first spacers are arranged on a side of the first insulated gate and on top of the source and drain regions, and an outer edge of the first spacers are flush with an outer edge of the source and drain regions.
A process for manufacturing a transistor with self-aligned double gates comprising the steps of:
- forming of a stack of layers onto a support substrate, the stack of layers including:
- a first gate layer,
- a first insulating gate layer,
- an active layer,
- a second insulating gate layer, and
- a second gate layer,
- defining an upper gate in the second gate layer,
- forming source and drain regions, self-aligned on the upper gate in the active layer,
- defining a lower gate, arranged between the support substrate and the active layer, and self-aligned on the upper gate, the defining of the upper gate being realized without previously roughing out the lower gate.
Dependencies are inferred from the claim text.