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US 7,018,942 B1Granted
Integrated circuit with improved RC delay
AssigneeCypress Semiconductor Corporation
InventorsMira Ben-Tzur, Krishnaswamy Ramkumar, Alain Blosse, Fuad Badrieh
Life of this patent
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Abstract
In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.
Claims20
A method of fabricating an integrated circuit, the method comprising:
- forming metal lines in a last metal level;
- forming a low-k dielectric layer over and between a first metal line and a second metal line, the low-k dielectric layer substantially filing a space extending between sidewalls of the first and second metal lines, the first and second metal lines being in the last metal level;
- and
- forming a passivation level over the last metal level such that the low-k dielectric layer remains over and between the first and second metal lines.
1 more element
A method of fabricating an integrated circuit, the method comprising:
- forming metal lines in a last metal level;
- and
- forming a passivation level over the metal lines, the passivation level comprising a low-k dielectric substantially filling a space between sidewalls of the metal lines, the low-k dielectric being over the metal lines.
A method of fabricating an integrated circuit, the method comprising:
- forming a last metal level over a dielectric layer;
- and
- forming a low-k dielectric layer over and between metal lines in the last metal level, the low-k dielectric layer being formed directly on the dielectric layer.
Dependencies are inferred from the claim text.