EEPROM device having selecting transistors and method of fabricating the same

A method of fabricating an EEPROM, comprising:

• forming a device isolation layer in a semiconductor substrate to define a plurality of active regions;
• forming a lower conductive pattern on each active region, wherein the lower conductive pattern extends to a portion of the device isolation layer substantially parallel to the active region;
• forming a dielectric pattern on the lower conductive pattern to include an opening extending across the active region;
• forming an upper conductive layer on the dielectric pattern;
• successively patterning the upper conductive layer and the dielectric pattern to form a control gate pattern extending across the active region and a selection gate pattern overlapping one sidewall of the opening, an inter-gate dielectric pattern self-aligned with the control gate pattern and a dummy dielectric pattern, wherein the dummy dielectric pattern is self-aligned with the one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern;
• and
• patterning the lower conductive pattern to form a lower gate pattern aligned with the selection gate pattern and a floating gate pattern self-aligned with the control gate pattern.