Latch-up prevention for memory cells
AssigneeMicron Technology, Inc.
InventorsJohn D. Porter, William N. Thompson
Life of this patent
Estimating the term…
Abstract
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.
Claims20
A method of fabricating a memory cell comprising the steps of:
- providing a substrate assembly having at least one semiconductor layer;
- forming a first semiconductor structure within said at least one semiconductor layer;
- forming a first source and a first drain of a first pull-up transistor in said first semiconductor structure;
- forming a second source and a second drain of a first pull-down transistor in said at least one semiconductor layer;
- forming a first contact and a second contact within said first semiconductor structure;
- forming a first gate for said first pull-up transistor and a second gate for said first pull-down transistor;
- coupling said first drain to said second drain;
- coupling said first gate to said second gate;
- and
- coupling said first source to one of said first and second contacts such that with the other of said first and second contacts coupled to a first voltage input said first source is coupled to said first voltage input through parasitic resistance of said first semiconductor structure.
A method of fabricating a memory cell comprising the steps of:
- providing a substrate assembly having at least one semiconductor layer;
- forming a first semiconductor structure and a second semiconductor structure within said at least one semiconductor layer;
- forming a first source and a first drain of a first pull-up transistor in said first semiconductor structure;
- forming a second source and a second drain of a first pull-down transistor in said at least one semiconductor layer;
- forming a third source and a third drain of a second pull-tip transistor in said second semiconductor structure;
- forming a fourth source and a fourth drain of a second pull-down transistor in said at least one semiconductor layer;
- forming a first contact and a second contact within said first semiconductor structure;
- forming a third contact and fourth contact within said second semiconductor structure;
- forming a first gate for said first pull-up transistor, a second gate for said first pull-down transistor, a third gate for said second pull-up transistor and a fourth gate for said second pull-down transistor;
- coupling said first drain to said second drain and said third drain to said fourth drain;
- coupling said first gate to said second gate and said third gate to said fourth gate;
- and
- coupling said first source to one of said first and second contacts such that with the other of said first and second contacts coupled to a first voltage input said first source is coupled to said first voltage input through parasitic resistance of said first semiconductor structure;
- and coupling said third source to one of said third and fourth contacts such that with the other of said third and fourth contacts coupled to said first voltage input said third source is coupled to said first voltage input through parasitic resistance of said second semiconductor structure.
Dependencies are inferred from the claim text.