Disposable hard mask for memory bitline scaling

A method of manufacturing a semiconductor memory device, the method comprising the steps of:

• forming a charge trapping layer over a substrate;
• forming a patterned hard mask layer over the charge trapping layer;
• forming doped regions of a first conductivity type in the substrate by implanting ion species through the charge trapping layer using the hard mask layer to define an implant pattern of the doped regions;
• laterally diffusing the doped regions into the substrate;
• and
• forming buried bitlines of a second conductivity type in the doped regions and the substrate by implanting ion species through the charge trapping layer using the hard mask layer to define an implant pattern of the bitlines so that the forming and diffusing steps result in laterally diffused doped regions adjacent each buried bitline that inhibit a leakage current between adjacent pairs of buried bitlines through substrate regions disposed between the diffused doped regions.